https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/80124
>From e3fb1fe7bdd4b7c24f9361c4d14dd1206fc8c067 Mon Sep 17 00:00:00 2001 From: wangpc <[email protected]> Date: Sun, 18 Feb 2024 11:12:16 +0800 Subject: [PATCH 1/4] Move after addIRPasses Created using spr 1.3.4 --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index fdf1c023fff87..7a26e1956424c 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -450,15 +450,15 @@ void RISCVPassConfig::addIRPasses() { if (EnableLoopDataPrefetch) addPass(createLoopDataPrefetchPass()); - if (EnableSelectOpt && getOptLevel() == CodeGenOptLevel::Aggressive) - addPass(createSelectOptimizePass()); - addPass(createRISCVGatherScatterLoweringPass()); addPass(createInterleavedAccessPass()); addPass(createRISCVCodeGenPreparePass()); } TargetPassConfig::addIRPasses(); + + if (getOptLevel() == CodeGenOptLevel::Aggressive && EnableSelectOpt) + addPass(createSelectOptimizePass()); } bool RISCVPassConfig::addPreISel() { >From 5d5398596dc30c47c67572ec20137fb3f9434940 Mon Sep 17 00:00:00 2001 From: wangpc <[email protected]> Date: Wed, 21 Feb 2024 21:21:28 +0800 Subject: [PATCH 2/4] Fix test Created using spr 1.3.4 --- llvm/test/CodeGen/RISCV/O3-pipeline.ll | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 62c1af52e6c20..8b52e3fe7b2f1 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -34,15 +34,6 @@ ; CHECK-NEXT: Optimization Remark Emitter ; CHECK-NEXT: Scalar Evolution Analysis ; CHECK-NEXT: Loop Data Prefetch -; CHECK-NEXT: Post-Dominator Tree Construction -; CHECK-NEXT: Branch Probability Analysis -; CHECK-NEXT: Block Frequency Analysis -; CHECK-NEXT: Lazy Branch Probability Analysis -; CHECK-NEXT: Lazy Block Frequency Analysis -; CHECK-NEXT: Optimization Remark Emitter -; CHECK-NEXT: Optimize selects -; CHECK-NEXT: Dominator Tree Construction -; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: RISC-V gather/scatter lowering ; CHECK-NEXT: Interleaved Access Pass ; CHECK-NEXT: RISC-V CodeGenPrepare @@ -77,6 +68,15 @@ ; CHECK-NEXT: Expand reduction intrinsics ; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: TLS Variable Hoist +; CHECK-NEXT: Post-Dominator Tree Construction +; CHECK-NEXT: Branch Probability Analysis +; CHECK-NEXT: Block Frequency Analysis +; CHECK-NEXT: Lazy Branch Probability Analysis +; CHECK-NEXT: Lazy Block Frequency Analysis +; CHECK-NEXT: Optimization Remark Emitter +; CHECK-NEXT: Optimize selects +; CHECK-NEXT: Dominator Tree Construction +; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: CodeGen Prepare ; CHECK-NEXT: Dominator Tree Construction ; CHECK-NEXT: Exception handling preparation >From 6d1a0d5ef4252067975cdb9d18d704b4650caa2b Mon Sep 17 00:00:00 2001 From: wangpc <[email protected]> Date: Fri, 23 Jan 2026 14:31:29 +0800 Subject: [PATCH 3/4] Disable the pass by default Created using spr 1.3.6-beta.1 --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/test/CodeGen/RISCV/O3-pipeline.ll | 11 +---------- 2 files changed, 2 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index aab86d11d7ebd..b408275e5e307 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -112,7 +112,7 @@ static cl::opt<bool> EnableCFIInstrInserter( static cl::opt<bool> EnableSelectOpt("riscv-select-opt", cl::Hidden, cl::desc("Enable select to branch optimizations"), - cl::init(true)); + cl::init(false)); extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target()); diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index f1b31d87013f2..3b63c1d86d3b1 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -72,19 +72,10 @@ ; CHECK-NEXT: Scalarize Masked Memory Intrinsics ; CHECK-NEXT: Expand reduction intrinsics ; CHECK-NEXT: Natural Loop Information -; CHECK-NEXT: Post-Dominator Tree Construction -; CHECK-NEXT: Branch Probability Analysis -; CHECK-NEXT: Block Frequency Analysis -; CHECK-NEXT: Lazy Branch Probability Analysis -; CHECK-NEXT: Lazy Block Frequency Analysis -; CHECK-NEXT: Optimization Remark Emitter -; CHECK-NEXT: Optimize selects -; CHECK-NEXT: Dominator Tree Construction -; CHECK-NEXT: Natural Loop Information ; CHECK-NEXT: Type Promotion ; CHECK-NEXT: CodeGen Prepare ; CHECK-NEXT: Dominator Tree Construction -; CHECK-NEXT: Exception handling preparation +; CHECK-NEXT: Exception handling preparation ; CHECK-NEXT: RISC-V Promote Constants ; CHECK-NEXT: A No-Op Barrier Pass ; CHECK-NEXT: FunctionPass Manager >From ff13eb7da2332ddab8342014f12e3fc6d2784cfb Mon Sep 17 00:00:00 2001 From: wangpc <[email protected]> Date: Mon, 26 Jan 2026 11:45:19 +0800 Subject: [PATCH 4/4] Refactor tests Created using spr 1.3.6-beta.1 --- llvm/test/CodeGen/RISCV/selectopt.ll | 124 ++++++++++----------------- 1 file changed, 47 insertions(+), 77 deletions(-) diff --git a/llvm/test/CodeGen/RISCV/selectopt.ll b/llvm/test/CodeGen/RISCV/selectopt.ll index bf896e2fa917a..e82037bb59e20 100644 --- a/llvm/test/CodeGen/RISCV/selectopt.ll +++ b/llvm/test/CodeGen/RISCV/selectopt.ll @@ -1,10 +1,13 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -select-optimize -mtriple=riscv64 -S < %s \ -; RUN: | FileCheck %s --check-prefix=NO-SELECT-OPT -; RUN: opt -select-optimize -mtriple=riscv64 -mattr=+enable-select-opt -S < %s \ -; RUN: | FileCheck %s --check-prefix=SELECT-OPT -; RUN: opt -select-optimize -mtriple=riscv64 -mattr=+enable-select-opt,+predictable-select-expensive -S < %s \ -; RUN: | FileCheck %s --check-prefix=SELECT-OPT +; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \ +; RUN: -mtriple=riscv64 -S < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,NO-SELECT-OPT +; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \ +; RUN: -mtriple=riscv64 -mattr=+enable-select-opt -S < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-NOT-EXPENSIVE +; RUN: opt -passes='require<profile-summary>,function(select-optimize)' \ +; RUN: -mtriple=riscv64 -mattr=+enable-select-opt,+predictable-select-expensive -S < %s \ +; RUN: | FileCheck %s --check-prefixes=CHECK,SELECT-OPT,SELECT-OPT-EXPENSIVE %struct.st = type { i32, i64, ptr, ptr, i16, ptr, ptr, i64, i64 } @@ -513,77 +516,41 @@ while.end: ; preds = %if.end87, %land.rhs ; This `or` is not transformed as it is not the last instruction in the block define i32 @or_notatendofblock(ptr nocapture noundef %x, i32 noundef %n, ptr nocapture noundef readonly %z) { -; NO-SELECT-OPT-LABEL: @or_notatendofblock( -; NO-SELECT-OPT-NEXT: entry: -; NO-SELECT-OPT-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[N:%.*]], 0 -; NO-SELECT-OPT-NEXT: br i1 [[CMP19]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] -; NO-SELECT-OPT: for.body.preheader: -; NO-SELECT-OPT-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 -; NO-SELECT-OPT-NEXT: br label [[FOR_BODY:%.*]] -; NO-SELECT-OPT: for.cond.cleanup: -; NO-SELECT-OPT-NEXT: [[Y_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[Y_1:%.*]], [[IF_END:%.*]] ] -; NO-SELECT-OPT-NEXT: ret i32 [[Y_0_LCSSA]] -; NO-SELECT-OPT: for.body: -; NO-SELECT-OPT-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END]] ] -; NO-SELECT-OPT-NEXT: [[Y_020:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[Y_1]], [[IF_END]] ] -; NO-SELECT-OPT-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i64 [[INDVARS_IV]] -; NO-SELECT-OPT-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -; NO-SELECT-OPT-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[Y_020]] -; NO-SELECT-OPT-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[ADD]], 0 -; NO-SELECT-OPT-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END]], label [[IF_THEN:%.*]] -; NO-SELECT-OPT: if.then: -; NO-SELECT-OPT-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, ptr [[Z:%.*]], i64 [[INDVARS_IV]] -; NO-SELECT-OPT-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 -; NO-SELECT-OPT-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]] -; NO-SELECT-OPT-NEXT: [[DIV1:%.*]] = sdiv i32 [[DIV]], [[TMP1]] -; NO-SELECT-OPT-NEXT: [[DIV2:%.*]] = sdiv i32 [[DIV1]], [[TMP1]] -; NO-SELECT-OPT-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[DIV2]], 0 -; NO-SELECT-OPT-NEXT: [[CONV:%.*]] = zext i1 [[CMP5]] to i32 -; NO-SELECT-OPT-NEXT: [[OR1:%.*]] = or i32 [[CONV]], [[ADD]] -; NO-SELECT-OPT-NEXT: [[OR:%.*]] = add i32 [[OR1]], 1 -; NO-SELECT-OPT-NEXT: br label [[IF_END]] -; NO-SELECT-OPT: if.end: -; NO-SELECT-OPT-NEXT: [[Y_1]] = phi i32 [ [[OR]], [[IF_THEN]] ], [ 0, [[FOR_BODY]] ] -; NO-SELECT-OPT-NEXT: store i32 [[Y_1]], ptr [[ARRAYIDX]], align 4 -; NO-SELECT-OPT-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; NO-SELECT-OPT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; NO-SELECT-OPT-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] -; -; SELECT-OPT-LABEL: @or_notatendofblock( -; SELECT-OPT-NEXT: entry: -; SELECT-OPT-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[N:%.*]], 0 -; SELECT-OPT-NEXT: br i1 [[CMP19]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] -; SELECT-OPT: for.body.preheader: -; SELECT-OPT-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 -; SELECT-OPT-NEXT: br label [[FOR_BODY:%.*]] -; SELECT-OPT: for.cond.cleanup: -; SELECT-OPT-NEXT: [[Y_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[Y_1:%.*]], [[IF_END:%.*]] ] -; SELECT-OPT-NEXT: ret i32 [[Y_0_LCSSA]] -; SELECT-OPT: for.body: -; SELECT-OPT-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END]] ] -; SELECT-OPT-NEXT: [[Y_020:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[Y_1]], [[IF_END]] ] -; SELECT-OPT-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i64 [[INDVARS_IV]] -; SELECT-OPT-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 -; SELECT-OPT-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[Y_020]] -; SELECT-OPT-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[ADD]], 0 -; SELECT-OPT-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END]], label [[IF_THEN:%.*]] -; SELECT-OPT: if.then: -; SELECT-OPT-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, ptr [[Z:%.*]], i64 [[INDVARS_IV]] -; SELECT-OPT-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 -; SELECT-OPT-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]] -; SELECT-OPT-NEXT: [[DIV1:%.*]] = sdiv i32 [[DIV]], [[TMP1]] -; SELECT-OPT-NEXT: [[DIV2:%.*]] = sdiv i32 [[DIV1]], [[TMP1]] -; SELECT-OPT-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[DIV2]], 0 -; SELECT-OPT-NEXT: [[CONV:%.*]] = zext i1 [[CMP5]] to i32 -; SELECT-OPT-NEXT: [[OR1:%.*]] = or i32 [[CONV]], [[ADD]] -; SELECT-OPT-NEXT: [[OR:%.*]] = add i32 [[OR1]], 1 -; SELECT-OPT-NEXT: br label [[IF_END]] -; SELECT-OPT: if.end: -; SELECT-OPT-NEXT: [[Y_1]] = phi i32 [ [[OR]], [[IF_THEN]] ], [ 0, [[FOR_BODY]] ] -; SELECT-OPT-NEXT: store i32 [[Y_1]], ptr [[ARRAYIDX]], align 4 -; SELECT-OPT-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 -; SELECT-OPT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] -; SELECT-OPT-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] +; CHECK-LABEL: @or_notatendofblock( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[N:%.*]], 0 +; CHECK-NEXT: br i1 [[CMP19]], label [[FOR_BODY_PREHEADER:%.*]], label [[FOR_COND_CLEANUP:%.*]] +; CHECK: for.body.preheader: +; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 +; CHECK-NEXT: br label [[FOR_BODY:%.*]] +; CHECK: for.cond.cleanup: +; CHECK-NEXT: [[Y_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[Y_1:%.*]], [[IF_END:%.*]] ] +; CHECK-NEXT: ret i32 [[Y_0_LCSSA]] +; CHECK: for.body: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[IF_END]] ] +; CHECK-NEXT: [[Y_020:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER]] ], [ [[Y_1]], [[IF_END]] ] +; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[X:%.*]], i64 [[INDVARS_IV]] +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], [[Y_020]] +; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[ADD]], 0 +; CHECK-NEXT: br i1 [[TOBOOL_NOT]], label [[IF_END]], label [[IF_THEN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i32, ptr [[Z:%.*]], i64 [[INDVARS_IV]] +; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX4]], align 4 +; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[DIV1:%.*]] = sdiv i32 [[DIV]], [[TMP1]] +; CHECK-NEXT: [[DIV2:%.*]] = sdiv i32 [[DIV1]], [[TMP1]] +; CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[DIV2]], 0 +; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP5]] to i32 +; CHECK-NEXT: [[OR1:%.*]] = or i32 [[CONV]], [[ADD]] +; CHECK-NEXT: [[OR:%.*]] = add i32 [[OR1]], 1 +; CHECK-NEXT: br label [[IF_END]] +; CHECK: if.end: +; CHECK-NEXT: [[Y_1]] = phi i32 [ [[OR]], [[IF_THEN]] ], [ 0, [[FOR_BODY]] ] +; CHECK-NEXT: store i32 [[Y_1]], ptr [[ARRAYIDX]], align 4 +; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[WIDE_TRIP_COUNT]] +; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY]] ; entry: %cmp19 = icmp sgt i32 %n, 0 @@ -986,3 +953,6 @@ latch: exit: ret void } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; SELECT-OPT-EXPENSIVE: {{.*}} +; SELECT-OPT-NOT-EXPENSIVE: {{.*}} _______________________________________________ llvm-branch-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
