================
@@ -1124,8 +1124,8 @@ SIRegisterInfo::getCrossCopyRegClass(const
TargetRegisterClass *RC) const {
return RC == &AMDGPU::SCC_CLASSRegClass ? &AMDGPU::SReg_32RegClass : RC;
}
-static unsigned getNumSubRegsForSpillOp(const MachineInstr &MI,
- const SIInstrInfo *TII) {
+unsigned SIRegisterInfo::getNumSubRegsForSpillOp(const MachineInstr &MI) const
{
----------------
arsenm wrote:
This really belongs in SIInstrInfo
https://github.com/llvm/llvm-project/pull/174997
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