https://github.com/arsenm created
https://github.com/llvm/llvm-project/pull/159234
AMDGPU: Ensure both wavesize features are not set
Make sure we cannot be in a mode with both wavesizes. This
prevents assertions in a future change. This should probably
just be an error, but we do not have a good way to report
errors from the MCSubtargetInfo constructor.
This breaks the assembler test which enables both, but this
behavior is not really useful. Maybe it's better to just delete
the test.
Convert wave_any test to update_mc_test_checks
update wave_any test
>From 41365e5cc69b3732c8bc8f1d138c3b6984e08e41 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 17 Sep 2025 02:00:48 +0900
Subject: [PATCH 1/3] AMDGPU: Ensure both wavesize features are not set
Make sure we cannot be in a mode with both wavesizes. This
prevents assertions in a future change. This should probably
just be an error, but we do not have a good way to report
errors from the MCSubtargetInfo constructor.
This breaks the assembler test which enables both, but this
behavior is not really useful. Maybe it's better to just delete
the test.
---
.../MCTargetDesc/AMDGPUMCTargetDesc.cpp | 16 +++++++++++--
.../wavesize-feature-unsupported-target.s | 23 +++++++++++++++++++
.../AMDGPU/gfx1250_wave64_feature.s | 13 +++++++++++
.../AMDGPU/gfx9_wave32_feature.txt | 13 +++++++++++
4 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/MC/AMDGPU/wavesize-feature-unsupported-target.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx1250_wave64_feature.s
create mode 100644 llvm/test/MC/Disassembler/AMDGPU/gfx9_wave32_feature.txt
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
index f2e2d0ed3f8a6..0ea5ad7ccaea4 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp
@@ -82,20 +82,32 @@ createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef
CPU, StringRef FS) {
MCSubtargetInfo *STI =
createAMDGPUMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
+ bool IsWave64 = STI->hasFeature(AMDGPU::FeatureWavefrontSize64);
+ bool IsWave32 = STI->hasFeature(AMDGPU::FeatureWavefrontSize32);
+
// FIXME: We should error for the default target.
if (STI->getFeatureBits().none())
STI->ToggleFeature(AMDGPU::FeatureSouthernIslands);
- if (!STI->hasFeature(AMDGPU::FeatureWavefrontSize64) &&
- !STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) {
+ if (!IsWave64 && !IsWave32) {
// If there is no default wave size it must be a generation before gfx10,
// these have FeatureWavefrontSize64 in their definition already. For
gfx10+
// set wave32 as a default.
STI->ToggleFeature(AMDGPU::isGFX10Plus(*STI)
? AMDGPU::FeatureWavefrontSize32
: AMDGPU::FeatureWavefrontSize64);
+ } else if (IsWave64 && IsWave32) {
+ // The wave size is mutually exclusive. If both somehow end up set, wave64
+ // wins.
+ //
+ // FIXME: This should really just be an error.
+ STI->ToggleFeature(AMDGPU::FeatureWavefrontSize32);
}
+ assert((STI->hasFeature(AMDGPU::FeatureWavefrontSize64) ^
+ STI->hasFeature(AMDGPU::FeatureWavefrontSize32)) &&
+ "wavesize features are mutually exclusive");
+
return STI;
}
diff --git a/llvm/test/MC/AMDGPU/wavesize-feature-unsupported-target.s
b/llvm/test/MC/AMDGPU/wavesize-feature-unsupported-target.s
new file mode 100644
index 0000000000000..8fc7b7fb05f0c
--- /dev/null
+++ b/llvm/test/MC/AMDGPU/wavesize-feature-unsupported-target.s
@@ -0,0 +1,23 @@
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+wavefrontsize64 -o - %s |
FileCheck -check-prefix=GFX1250 %s
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -mattr=+wavefrontsize32 -o - %s |
FileCheck -check-prefix=GFX900 %s
+
+// Both are supported, but not at the same time
+// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010
-mattr=+wavefrontsize32,+wavefrontsize64 %s | FileCheck -check-prefixes=GFX10 %s
+
+// Test that there is no assertion when using an explicit
+// wavefrontsize attribute on a target which does not support it.
+
+// GFX1250: v_add_f64_e32 v[0:1], 1.0, v[0:1]
+// GFX900: v_add_f64 v[0:1], 1.0, v[0:1]
+// GFX10: v_add_f64 v[0:1], 1.0, v[0:1]
+v_add_f64 v[0:1], 1.0, v[0:1]
+
+// GFX1250: v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+// GFX900: v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+// GFX10: v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+
+// GFX1250: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+// GFX900: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+// GFX10: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+v_cndmask_b32 v1, v2, v3, s[0:1]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx1250_wave64_feature.s
b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_wave64_feature.s
new file mode 100644
index 0000000000000..bdea636a9efe3
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx1250_wave64_feature.s
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -mattr=+wavefrontsize64
-disassemble -o - %s | FileCheck %s
+
+# Make sure there's no assertion when trying to use an unsupported
+# wave64 on a wave32-only target
+
+# CHECK: v_add_f64_e32 v[0:1], 1.0, v[0:1]
+0xf2,0x00,0x00,0x04
+
+# CHECK: v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+0x00,0x00,0x4a,0xd4,0xf2,0x02,0x00,0x00
+
+# CHECK: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+0x01,0x00,0x01,0xd5,0x02,0x07,0x02,0x00
diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx9_wave32_feature.txt
b/llvm/test/MC/Disassembler/AMDGPU/gfx9_wave32_feature.txt
new file mode 100644
index 0000000000000..40494b3dfa1ea
--- /dev/null
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx9_wave32_feature.txt
@@ -0,0 +1,13 @@
+# RUN: llvm-mc -triple=amdgcn -mcpu=gfx900 -mattr=+wavefrontsize32
-disassemble -o - %s | FileCheck %s
+
+# Make sure there's no assertion when trying to use an unsupported
+# wave32 on a wave64-only target
+
+# CHECK: v_add_f64 v[0:1], 1.0, v[0:1]
+0x00,0x00,0x80,0xd2,0xf2,0x00,0x02,0x00
+
+# CHECK: v_cmp_eq_u32_e64 s[0:1], 1.0, s1
+0x00,0x00,0xca,0xd0,0xf2,0x02,0x00,0x00
+
+# CHECK: v_cndmask_b32_e64 v1, v2, v3, s[0:1]
+0x01,0x00,0x00,0xd1,0x02,0x07,0x02,0x00
>From a016959f426c0dd71e0aaaba40cfdcb8d167a2c0 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 17 Sep 2025 11:44:35 +0900
Subject: [PATCH 2/3] Convert wave_any test to update_mc_test_checks
---
llvm/test/MC/AMDGPU/wave_any.s | 57 +++++++++++++++++-----------------
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/llvm/test/MC/AMDGPU/wave_any.s b/llvm/test/MC/AMDGPU/wave_any.s
index 27502eff89bfc..3c265db30a324 100644
--- a/llvm/test/MC/AMDGPU/wave_any.s
+++ b/llvm/test/MC/AMDGPU/wave_any.s
@@ -1,13 +1,14 @@
+// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py
UTC_ARGS: --version 6
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010
-mattr=+wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck
--check-prefix=GFX10 %s
v_cmp_ge_i32_e32 s0, v0
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v0 ; encoding: [0x00,0x00,0x0c,0x7d]
+// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x0c,0x7d]
v_cmp_ge_i32_e32 vcc_lo, s0, v1
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v1 ; encoding: [0x00,0x02,0x0c,0x7d]
+// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v1 ; encoding:
[0x00,0x02,0x0c,0x7d]
v_cmp_ge_i32_e32 vcc, s0, v2
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v2 ; encoding: [0x00,0x04,0x0c,0x7d]
+// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v2 ; encoding:
[0x00,0x04,0x0c,0x7d]
v_cmp_le_f16_sdwa s0, v3, v4 src0_sel:WORD_1 src1_sel:DWORD
// GFX10: v_cmp_le_f16_sdwa s0, v3, v4 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x08,0x96,0x7d,0x03,0x80,0x05,0x06]
@@ -16,10 +17,10 @@ v_cmp_le_f16_sdwa s[0:1], v3, v4 src0_sel:WORD_1
src1_sel:DWORD
// GFX10: v_cmp_le_f16_sdwa s[0:1], v3, v4 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x08,0x96,0x7d,0x03,0x80,0x05,0x06]
v_cmp_class_f32_e32 vcc_lo, s0, v0
-// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding: [0x00,0x00,0x10,0x7d]
+// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x10,0x7d]
v_cmp_class_f32_e32 vcc, s0, v0
-// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding: [0x00,0x00,0x10,0x7d]
+// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x10,0x7d]
v_cmp_class_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
// GFX10: v_cmp_class_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
@@ -34,13 +35,13 @@ v_cmp_class_f16_sdwa s[0:1], v1, v2 src0_sel:DWORD
src1_sel:DWORD
// GFX10: v_cmp_class_f16_sdwa s[0:1], v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x80,0x06,0x06]
v_cndmask_b32_e32 v1, v2, v3,
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
v_cndmask_b32_e32 v1, v2, v3, vcc
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
// GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x50]
@@ -127,61 +128,61 @@ v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc
quad_perm:[0,1,2,3] row_mask:0x0 ban
// GFX10: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
v_add_co_u32 v0, s0, v0, v2
-// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_ci_u32_e64 v4, s0, v1, v5, s2
-// GFX10: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
v_sub_co_u32 v0, s0, v0, v2
-// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
v_sub_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2
-// GFX10: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
v_subrev_co_u32 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
v_subrev_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2
// GFX10: v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
v_add_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_u32 v0, exec, v0, v2
-// GFX10: v_add_co_u32 v0, exec, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, exec, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_u32 v0, exec_lo, v0, v2
-// GFX10: v_add_co_u32 v0, exec_lo, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, exec_lo, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
// GFX10: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
v_sub_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
v_sub_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
// GFX10: v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding:
[0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
v_subrev_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
v_subrev_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
// GFX10: v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding:
[0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
@@ -199,10 +200,10 @@ v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, vcc
// GFX10: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, vcc ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0xaa,0x01]
v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX10: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
+// GFX10: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
v_div_scale_f32 v2, s[2:3], v0, v0, v2
-// GFX10: v_div_scale_f32 v2, s[2:3], v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
+// GFX10: v_div_scale_f32 v2, s[2:3], v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
v_div_scale_f64 v[2:3], s2, v[0:1], v[0:1], v[2:3]
// GFX10: v_div_scale_f64 v[2:3], s2, v[0:1], v[0:1], v[2:3] ; encoding:
[0x02,0x02,0x6e,0xd5,0x00,0x01,0x0a,0x04]
@@ -223,7 +224,7 @@ v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
// GFX10: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3] ; encoding:
[0x00,0x06,0x76,0xd5,0x00,0x03,0x0a,0x04]
v_cmpx_neq_f32_e32 v0, v1
-// GFX10: v_cmpx_neq_f32_e32 v0, v1 ; encoding: [0x00,0x03,0x3a,0x7c]
+// GFX10: v_cmpx_neq_f32_e32 v0, v1 ; encoding:
[0x00,0x03,0x3a,0x7c]
v_cmpx_neq_f32_sdwa v0, v1 src0_sel:WORD_1 src1_sel:DWORD
// GFX10: v_cmpx_neq_f32_sdwa v0, v1 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x02,0x3a,0x7c,0x00,0x00,0x05,0x06]
@@ -232,7 +233,7 @@ v_cmpx_eq_u32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
// GFX10: v_cmpx_eq_u32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD ; encoding:
[0xf9,0x02,0xa5,0x7d,0x00,0x00,0x05,0x86]
v_cmpx_class_f32_e64 v0, 1
-// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding:
[0x7e,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
+// GFX10: v_cmpx_class_f32_e64 v0, 1 ; encoding:
[0x7e,0x00,0x98,0xd4,0x00,0x03,0x01,0x00]
v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD
// GFX10: v_cmpx_class_f32_sdwa v0, 1 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x02,0x31,0x7d,0x00,0x00,0x05,0x86]
>From 50bdbb44f797f15b2c151e6ee8c1751aaf4e9f47 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Wed, 17 Sep 2025 11:46:11 +0900
Subject: [PATCH 3/3] update wave_any test
---
llvm/test/MC/AMDGPU/wave_any.s | 101 +++++++++++++++++----------------
1 file changed, 51 insertions(+), 50 deletions(-)
diff --git a/llvm/test/MC/AMDGPU/wave_any.s b/llvm/test/MC/AMDGPU/wave_any.s
index 3c265db30a324..15b235a92d68e 100644
--- a/llvm/test/MC/AMDGPU/wave_any.s
+++ b/llvm/test/MC/AMDGPU/wave_any.s
@@ -1,158 +1,159 @@
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py
UTC_ARGS: --version 6
-// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1010
-mattr=+wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck
--check-prefix=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010
-mattr=+wavefrontsize32,+wavefrontsize64 -show-encoding %s | FileCheck
--check-prefixes=GFX10 %s
+// RUN: not llvm-mc -triple=amdgcn -mcpu=gfx1010
-mattr=+wavefrontsize32,+wavefrontsize64 -filetype=null %s 2>&1 | FileCheck
-implicit-check-not=error: --check-prefixes=GFX10-ERR %s
v_cmp_ge_i32_e32 s0, v0
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x0c,0x7d]
+// GFX10: v_cmp_ge_i32_e32 vcc, s0, v0 ; encoding:
[0x00,0x00,0x0c,0x7d]
v_cmp_ge_i32_e32 vcc_lo, s0, v1
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v1 ; encoding:
[0x00,0x02,0x0c,0x7d]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_cmp_ge_i32_e32 vcc, s0, v2
-// GFX10: v_cmp_ge_i32_e32 vcc_lo, s0, v2 ; encoding:
[0x00,0x04,0x0c,0x7d]
+// GFX10: v_cmp_ge_i32_e32 vcc, s0, v2 ; encoding:
[0x00,0x04,0x0c,0x7d]
v_cmp_le_f16_sdwa s0, v3, v4 src0_sel:WORD_1 src1_sel:DWORD
-// GFX10: v_cmp_le_f16_sdwa s0, v3, v4 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x08,0x96,0x7d,0x03,0x80,0x05,0x06]
+// GFX10-ERR: :[[@LINE-1]]:19: error: invalid operand for instruction
v_cmp_le_f16_sdwa s[0:1], v3, v4 src0_sel:WORD_1 src1_sel:DWORD
// GFX10: v_cmp_le_f16_sdwa s[0:1], v3, v4 src0_sel:WORD_1 src1_sel:DWORD ;
encoding: [0xf9,0x08,0x96,0x7d,0x03,0x80,0x05,0x06]
v_cmp_class_f32_e32 vcc_lo, s0, v0
-// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x10,0x7d]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_cmp_class_f32_e32 vcc, s0, v0
-// GFX10: v_cmp_class_f32_e32 vcc_lo, s0, v0 ; encoding:
[0x00,0x00,0x10,0x7d]
+// GFX10: v_cmp_class_f32_e32 vcc, s0, v0 ; encoding:
[0x00,0x00,0x10,0x7d]
v_cmp_class_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: v_cmp_class_f16_sdwa vcc_lo, v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
+// GFX10-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD
// GFX10: v_cmp_class_f16_sdwa vcc, v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x00,0x06,0x06]
v_cmp_class_f16_sdwa s0, v1, v2 src0_sel:DWORD src1_sel:DWORD
-// GFX10: v_cmp_class_f16_sdwa s0, v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x80,0x06,0x06]
+// GFX10-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
v_cmp_class_f16_sdwa s[0:1], v1, v2 src0_sel:DWORD src1_sel:DWORD
// GFX10: v_cmp_class_f16_sdwa s[0:1], v1, v2 src0_sel:DWORD src1_sel:DWORD ;
encoding: [0xf9,0x04,0x1e,0x7d,0x01,0x80,0x06,0x06]
v_cndmask_b32_e32 v1, v2, v3,
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding:
[0x02,0x07,0x02,0x02]
v_cndmask_b32_e32 v1, v2, v3, vcc_lo
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_cndmask_b32_e32 v1, v2, v3, vcc
-// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc_lo ; encoding:
[0x02,0x07,0x02,0x02]
+// GFX10: v_cndmask_b32_e32 v1, v2, v3, vcc ; encoding:
[0x02,0x07,0x02,0x02]
v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
-// GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x50]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_add_co_ci_u32_e32 v3, vcc, v3, v4, vcc
-// GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x50]
+// GFX10: v_add_co_ci_u32_e32 v3, vcc, v3, v4, vcc ; encoding:
[0x03,0x09,0x06,0x50]
v_add_co_ci_u32_e32 v3, v3, v4
-// GFX10: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x50]
+// GFX10: v_add_co_ci_u32_e32 v3, vcc, v3, v4, vcc ; encoding:
[0x03,0x09,0x06,0x50]
v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
-// GFX10: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x52]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_sub_co_ci_u32_e32 v3, vcc, v3, v4, vcc
-// GFX10: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x52]
+// GFX10: v_sub_co_ci_u32_e32 v3, vcc, v3, v4, vcc ; encoding:
[0x03,0x09,0x06,0x52]
v_sub_co_ci_u32_e32 v3, v3, v4
-// GFX10: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo ; encoding:
[0x03,0x09,0x06,0x52]
+// GFX10: v_sub_co_ci_u32_e32 v3, vcc, v3, v4, vcc ; encoding:
[0x03,0x09,0x06,0x52]
v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-// GFX10: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; encoding:
[0x80,0x02,0x02,0x54]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_subrev_co_ci_u32_e32 v1, vcc, 0, v1, vcc
-// GFX10: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; encoding:
[0x80,0x02,0x02,0x54]
+// GFX10: v_subrev_co_ci_u32_e32 v1, vcc, 0, v1, vcc ; encoding:
[0x80,0x02,0x02,0x54]
v_subrev_co_ci_u32_e32 v1, 0, v1
-// GFX10: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo ; encoding:
[0x80,0x02,0x02,0x54]
+// GFX10: v_subrev_co_ci_u32_e32 v1, vcc, 0, v1, vcc ; encoding:
[0x80,0x02,0x02,0x54]
v_add_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_add_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x00,0x06]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_add_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
// GFX10: v_add_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x00,0x06]
v_add_co_ci_u32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_add_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x00,0x06]
+// GFX10: v_add_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x00,0x06]
v_sub_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_sub_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x52,0x01,0x06,0x00,0x06]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_sub_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
// GFX10: v_sub_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x52,0x01,0x06,0x00,0x06]
v_sub_co_ci_u32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_sub_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x52,0x01,0x06,0x00,0x06]
+// GFX10: v_sub_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x52,0x01,0x06,0x00,0x06]
v_subrev_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_subrev_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x54,0x01,0x06,0x00,0x06]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_subrev_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
// GFX10: v_subrev_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x54,0x01,0x06,0x00,0x06]
v_subrev_co_ci_u32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_subrev_co_ci_u32_sdwa v1, vcc_lo, v1, v4, vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x54,0x01,0x06,0x00,0x06]
+// GFX10: v_subrev_co_ci_u32_sdwa v1, vcc, v1, v4, vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x54,0x01,0x06,0x00,0x06]
v_add_co_ci_u32 v1, sext(v1), sext(v4) dst_sel:DWORD dst_unused:UNUSED_PAD
src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_add_co_ci_u32_sdwa v1, vcc_lo, sext(v1), sext(v4), vcc_lo
dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x08,0x0e]
+// GFX10: v_add_co_ci_u32_sdwa v1, vcc, sext(v1), sext(v4), vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x08,0x0e]
v_add_co_ci_u32_sdwa v1, vcc_lo, sext(v1), sext(v4), vcc_lo dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-// GFX10: v_add_co_ci_u32_sdwa v1, vcc_lo, sext(v1), sext(v4), vcc_lo
dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x08,0x0e]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_add_co_ci_u32_sdwa v1, vcc, sext(v1), sext(v4), vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
// GFX10: v_add_co_ci_u32_sdwa v1, vcc, sext(v1), sext(v4), vcc dst_sel:DWORD
dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD ; encoding:
[0xf9,0x08,0x02,0x50,0x01,0x06,0x08,0x0e]
v_add_co_ci_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
-// GFX10: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
+// GFX10: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0
-// GFX10: v_add_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
bank_mask:0x0
// GFX10: v_add_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x50,0x01,0xe4,0x00,0x00]
v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0
-// GFX10: v_sub_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
bank_mask:0x0
// GFX10: v_sub_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00]
v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0
-// GFX10: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo
quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding:
[0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
+// GFX10-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or
mode
v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0
bank_mask:0x0
// GFX10: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3]
row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
v_add_co_u32 v0, s0, v0, v2
-// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:18: error: invalid operand for instruction
v_add_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
v_add_co_ci_u32_e64 v4, s0, v1, v5, s2
-// GFX10: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_sub_co_u32 v0, s0, v0, v2
-// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:18: error: invalid operand for instruction
v_sub_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2
-// GFX10: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_subrev_co_u32 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:21: error: invalid operand for instruction
v_subrev_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding:
[0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2
-// GFX10: v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding:
[0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
v_add_co_u32 v0, s[0:1], v0, v2
// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
@@ -161,7 +162,7 @@ v_add_co_u32 v0, exec, v0, v2
// GFX10: v_add_co_u32 v0, exec, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
v_add_co_u32 v0, exec_lo, v0, v2
-// GFX10: v_add_co_u32 v0, exec_lo, v0, v2 ; encoding:
[0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10-ERR: :[[@LINE-1]]:18: error: invalid operand for instruction
v_add_co_u32_e64 v0, s[0:1], v0, v2
// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding:
[0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
@@ -188,37 +189,37 @@ v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
// GFX10: v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding:
[0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2
-// GFX10: v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2 ; encoding:
[0x04,0x6a,0x28,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s[2:3]
-// GFX10: v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s[2:3] ; encoding:
[0x04,0x6a,0x28,0xd5,0x01,0x0b,0x0a,0x00]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_add_co_ci_u32_e64 v4, s0, v1, v5, vcc_lo
-// GFX10: v_add_co_ci_u32_e64 v4, s0, v1, v5, vcc_lo ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0xaa,0x01]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, vcc
// GFX10: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, vcc ; encoding:
[0x04,0x00,0x28,0xd5,0x01,0x0b,0xaa,0x01]
v_div_scale_f32 v2, s2, v0, v0, v2
-// GFX10: v_div_scale_f32 v2, s2, v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
+// GFX10-ERR: :[[@LINE-1]]:21: error: invalid operand for instruction
v_div_scale_f32 v2, s[2:3], v0, v0, v2
// GFX10: v_div_scale_f32 v2, s[2:3], v0, v0, v2 ; encoding:
[0x02,0x02,0x6d,0xd5,0x00,0x01,0x0a,0x04]
v_div_scale_f64 v[2:3], s2, v[0:1], v[0:1], v[2:3]
-// GFX10: v_div_scale_f64 v[2:3], s2, v[0:1], v[0:1], v[2:3] ; encoding:
[0x02,0x02,0x6e,0xd5,0x00,0x01,0x0a,0x04]
+// GFX10-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], v[2:3]
// GFX10: v_div_scale_f64 v[2:3], s[2:3], v[0:1], v[0:1], v[2:3] ; encoding:
[0x02,0x02,0x6e,0xd5,0x00,0x01,0x0a,0x04]
v_mad_i64_i32 v[0:1], s6, v0, v1, v[2:3]
-// GFX10: v_mad_i64_i32 v[0:1], s6, v0, v1, v[2:3] ; encoding:
[0x00,0x06,0x77,0xd5,0x00,0x03,0x0a,0x04]
+// GFX10-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3]
// GFX10: v_mad_i64_i32 v[0:1], s[6:7], v0, v1, v[2:3] ; encoding:
[0x00,0x06,0x77,0xd5,0x00,0x03,0x0a,0x04]
v_mad_u64_u32 v[0:1], s6, v0, v1, v[2:3]
-// GFX10: v_mad_u64_u32 v[0:1], s6, v0, v1, v[2:3] ; encoding:
[0x00,0x06,0x76,0xd5,0x00,0x03,0x0a,0x04]
+// GFX10-ERR: :[[@LINE-1]]:23: error: invalid operand for instruction
v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3]
// GFX10: v_mad_u64_u32 v[0:1], s[6:7], v0, v1, v[2:3] ; encoding:
[0x00,0x06,0x76,0xd5,0x00,0x03,0x0a,0x04]
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
