https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/153926
Backport 76d993bd25ff462d915f69772454e7b1ca42fdb8
Requested by: @androm3da
>From 27a00648607f22b4b2d1de4adb72fe6364a7ef88 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <baranniko...@gmail.com>
Date: Sat, 16 Aug 2025 05:13:43 +0300
Subject: [PATCH] [Hexagon] Add missing operand when disassembling Y4_crswap10
(#153849)
Auto-generated decoder fails to add the $sgp10 operand because it has no
encoding bits.
Work around this by adding the missing operand after decoding is
complete.
Fixes #153829.
(cherry picked from commit 76d993bd25ff462d915f69772454e7b1ca42fdb8)
---
llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp | 3 +++
llvm/test/MC/Hexagon/system-inst.s | 3 +++
2 files changed, 6 insertions(+)
diff --git a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
index 22cff7c80fa01..bcddb540d35dc 100644
--- a/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
+++ b/llvm/lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
@@ -526,6 +526,9 @@ DecodeStatus
HexagonDisassembler::getSingleInstruction(MCInst &MI, MCInst &MCB,
MI.insert(MI.begin() + 1,
MCOperand::createExpr(MCConstantExpr::create(-1, getContext())));
break;
+ case Hexagon::Y4_crswap10:
+ MI.addOperand(MCOperand::createReg(Hexagon::SGP1_0));
+ break;
default:
break;
}
diff --git a/llvm/test/MC/Hexagon/system-inst.s
b/llvm/test/MC/Hexagon/system-inst.s
index 7bc1533598532..07f7ca0acb2dc 100644
--- a/llvm/test/MC/Hexagon/system-inst.s
+++ b/llvm/test/MC/Hexagon/system-inst.s
@@ -89,6 +89,9 @@ crswap(r12,sgp0)
#CHECK: 652dc000 { crswap(r13,sgp1) }
crswap(r13,sgp1)
+#CHECK: 6d8ec000 { crswap(r15:14,s1:0) }
+crswap(r15:14,sgp1:0)
+
#CHECK: 660fc00e { r14 = getimask(r15) }
r14=getimask(r15)
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