https://github.com/shiltian updated https://github.com/llvm/llvm-project/pull/149631
>From d362ce6e616be7b0e1316fae1e3bcae8c12ff5aa Mon Sep 17 00:00:00 2001 From: Shilei Tian <i...@tianshilei.me> Date: Fri, 18 Jul 2025 21:52:34 -0400 Subject: [PATCH] [AMDGPU] Add the code generation support for `llvm.[sin/cos].bf16` This is a partial support because some other instructions have not been upstreamed yet. --- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 2 +- llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll | 38 +++++++++++++++++++++++ llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll | 38 +++++++++++++++++++++++ 3 files changed, 77 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 03cebc8ed224d..bc0fd8d4e814b 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -620,7 +620,7 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM, // BF16 - VOP1 Actions. if (Subtarget->hasBF16TransInsts()) - setOperationAction(ISD::FDIV, MVT::bf16, Custom); + setOperationAction({ISD::FCOS, ISD::FSIN, ISD::FDIV}, MVT::bf16, Custom); setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, MVT::f16, Promote); setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, MVT::bf16, Promote); diff --git a/llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll new file mode 100644 index 0000000000000..ced96ee98e0ad --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.cos.bf16.ll @@ -0,0 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 %s -o - | FileCheck -check-prefixes=GCN %s +; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + +; FIXME: GlobalISel does not work with bf16 + +declare bfloat @llvm.cos.bf16(bfloat) #0 + +define amdgpu_kernel void @cos_bf16_constant_4(ptr addrspace(1) %out) #1 { +; GCN-LABEL: cos_bf16_constant_4: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GCN-NEXT: v_cos_bf16_e32 v0, 0x3f23 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: global_store_b16 v1, v0, s[0:1] +; GCN-NEXT: s_endpgm + %cos = call bfloat @llvm.cos.bf16(bfloat 4.0) #0 + store bfloat %cos, ptr addrspace(1) %out, align 2 + ret void +} + +define amdgpu_kernel void @cos_bf16_constant_100(ptr addrspace(1) %out) #1 { +; GCN-LABEL: cos_bf16_constant_100: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GCN-NEXT: v_cos_bf16_e32 v0, 0x417f +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: global_store_b16 v1, v0, s[0:1] +; GCN-NEXT: s_endpgm + %cos = call bfloat @llvm.cos.bf16(bfloat 100.0) #0 + store bfloat %cos, ptr addrspace(1) %out, align 2 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll new file mode 100644 index 0000000000000..7a355a36b15bf --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.sin.bf16.ll @@ -0,0 +1,38 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 +; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 %s -o - | FileCheck -check-prefixes=GCN %s +; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s + +; FIXME: GlobalISel does not work with bf16 + +declare bfloat @llvm.sin.bf16(bfloat) #0 + +define amdgpu_kernel void @sin_bf16_constant_4(ptr addrspace(1) %out) #1 { +; GCN-LABEL: sin_bf16_constant_4: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GCN-NEXT: v_sin_bf16_e32 v0, 0x3f23 +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: global_store_b16 v1, v0, s[0:1] +; GCN-NEXT: s_endpgm + %sin = call bfloat @llvm.sin.bf16(bfloat 4.0) #0 + store bfloat %sin, ptr addrspace(1) %out, align 2 + ret void +} + +define amdgpu_kernel void @sin_bf16_constant_100(ptr addrspace(1) %out) #1 { +; GCN-LABEL: sin_bf16_constant_100: +; GCN: ; %bb.0: +; GCN-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; GCN-NEXT: v_sin_bf16_e32 v0, 0x417f +; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: global_store_b16 v1, v0, s[0:1] +; GCN-NEXT: s_endpgm + %sin = call bfloat @llvm.sin.bf16(bfloat 100.0) #0 + store bfloat %sin, ptr addrspace(1) %out, align 2 + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits