llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) <details> <summary>Changes</summary> Backport 84e689b Requested by: @<!-- -->svs-quic --- Full diff: https://github.com/llvm/llvm-project/pull/149770.diff 2 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td (+2-2) - (modified) llvm/test/CodeGen/RISCV/xqciac.ll (+19-19) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index c7cb6e237aeac..f39130090defd 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -1377,9 +1377,9 @@ let Predicates = [HasVendorXqciac, IsRV32] in { def : Pat<(i32 (add GPRNoX0:$rd, (mul GPRNoX0:$rs1, simm12:$imm12))), (QC_MULIADD GPRNoX0:$rd, GPRNoX0:$rs1, simm12:$imm12)>; def : Pat<(i32 (add_like_non_imm12 (shl GPRNoX0:$rs1, uimm5gt3:$imm), GPRNoX0:$rs2)), - (QC_SHLADD GPRNoX0:$rs2, GPRNoX0:$rs1, uimm5gt3:$imm)>; + (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>; def : Pat<(i32 (riscv_shl_add GPRNoX0:$rs1, uimm5gt3:$imm, GPRNoX0:$rs2)), - (QC_SHLADD GPRNoX0:$rs2, GPRNoX0:$rs1, uimm5gt3:$imm)>; + (QC_SHLADD GPRNoX0:$rs1, GPRNoX0:$rs2, uimm5gt3:$imm)>; } // Predicates = [HasVendorXqciac, IsRV32] /// Simple arithmetic operations diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll index a3b4e7829a51d..4c77b391a47da 100644 --- a/llvm/test/CodeGen/RISCV/xqciac.ll +++ b/llvm/test/CodeGen/RISCV/xqciac.ll @@ -231,12 +231,12 @@ define dso_local i32 @pow2(i32 %a, i32 %b) local_unnamed_addr #0 { ; ; RV32IMXQCIAC-LABEL: pow2: ; RV32IMXQCIAC: # %bb.0: # %entry -; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: pow2: ; RV32IZBAMXQCIAC: # %bb.0: # %entry -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5 ; RV32IZBAMXQCIAC-NEXT: ret entry: %mul = mul nsw i32 %b, 32 @@ -276,12 +276,12 @@ define dso_local i32 @shladd(i32 %a, i32 %b) local_unnamed_addr #0 { ; ; RV32IMXQCIAC-LABEL: shladd: ; RV32IMXQCIAC: # %bb.0: # %entry -; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shladd: ; RV32IZBAMXQCIAC: # %bb.0: # %entry -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31 ; RV32IZBAMXQCIAC-NEXT: ret entry: %shl = shl nsw i32 %b, 31 @@ -305,9 +305,9 @@ define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 { ; RV32IMXQCIAC-LABEL: shladd64: ; RV32IMXQCIAC: # %bb.0: # %entry ; RV32IMXQCIAC-NEXT: srli a4, a2, 1 -; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a2, 31 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31 ; RV32IMXQCIAC-NEXT: slli a2, a2, 31 -; RV32IMXQCIAC-NEXT: qc.shladd a3, a4, a3, 31 +; RV32IMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31 ; RV32IMXQCIAC-NEXT: sltu a2, a0, a2 ; RV32IMXQCIAC-NEXT: add a1, a1, a3 ; RV32IMXQCIAC-NEXT: add a1, a1, a2 @@ -316,9 +316,9 @@ define dso_local i64 @shladd64(i64 %a, i64 %b) local_unnamed_addr #0 { ; RV32IZBAMXQCIAC-LABEL: shladd64: ; RV32IZBAMXQCIAC: # %bb.0: # %entry ; RV32IZBAMXQCIAC-NEXT: srli a4, a2, 1 -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a2, 31 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a2, a0, 31 ; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 31 -; RV32IZBAMXQCIAC-NEXT: qc.shladd a3, a4, a3, 31 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a3, a3, a4, 31 ; RV32IZBAMXQCIAC-NEXT: sltu a2, a0, a2 ; RV32IZBAMXQCIAC-NEXT: add a1, a1, a3 ; RV32IZBAMXQCIAC-NEXT: add a1, a1, a2 @@ -338,12 +338,12 @@ define dso_local i32 @shladd_ordisjoint(i32 %a, i32 %b) local_unnamed_addr #0 { ; ; RV32IMXQCIAC-LABEL: shladd_ordisjoint: ; RV32IMXQCIAC: # %bb.0: # %entry -; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 22 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shladd_ordisjoint: ; RV32IZBAMXQCIAC: # %bb.0: # %entry -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 22 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 22 ; RV32IZBAMXQCIAC-NEXT: ret entry: %shl = shl nsw i32 %b, 22 @@ -361,13 +361,13 @@ define dso_local i32 @shladdc1c2(i32 %a, i32 %b) local_unnamed_addr #0 { ; ; RV32IMXQCIAC-LABEL: shladdc1c2: ; RV32IMXQCIAC: # %bb.0: # %entry -; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5 ; RV32IMXQCIAC-NEXT: slli a0, a0, 26 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shladdc1c2: ; RV32IZBAMXQCIAC: # %bb.0: # %entry -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 5 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 5 ; RV32IZBAMXQCIAC-NEXT: slli a0, a0, 26 ; RV32IZBAMXQCIAC-NEXT: ret entry: @@ -388,7 +388,7 @@ define dso_local i32 @shxaddc1c2(i32 %a, i32 %b) local_unnamed_addr #0 { ; RV32IMXQCIAC-LABEL: shxaddc1c2: ; RV32IMXQCIAC: # %bb.0: # %entry ; RV32IMXQCIAC-NEXT: slli a1, a1, 28 -; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 31 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 31 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shxaddc1c2: @@ -417,18 +417,18 @@ define dso_local i64 @shladdc1c264(i64 %a, i64 %b) local_unnamed_addr #0 { ; RV32IMXQCIAC-LABEL: shladdc1c264: ; RV32IMXQCIAC: # %bb.0: # %entry ; RV32IMXQCIAC-NEXT: srli a1, a2, 12 -; RV32IMXQCIAC-NEXT: qc.shladd a1, a1, a3, 20 +; RV32IMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20 ; RV32IMXQCIAC-NEXT: slli a2, a2, 20 -; RV32IMXQCIAC-NEXT: qc.shladd a1, a1, a0, 23 +; RV32IMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23 ; RV32IMXQCIAC-NEXT: mv a0, a2 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shladdc1c264: ; RV32IZBAMXQCIAC: # %bb.0: # %entry ; RV32IZBAMXQCIAC-NEXT: srli a1, a2, 12 -; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a1, a3, 20 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a3, a1, 20 ; RV32IZBAMXQCIAC-NEXT: slli a2, a2, 20 -; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a1, a0, 23 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a1, a0, a1, 23 ; RV32IZBAMXQCIAC-NEXT: mv a0, a2 ; RV32IZBAMXQCIAC-NEXT: ret entry: @@ -449,13 +449,13 @@ define dso_local i32 @shladdc1equalc2(i32 %a, i32 %b) local_unnamed_addr #0 { ; RV32IMXQCIAC-LABEL: shladdc1equalc2: ; RV32IMXQCIAC: # %bb.0: # %entry ; RV32IMXQCIAC-NEXT: slli a1, a1, 12 -; RV32IMXQCIAC-NEXT: qc.shladd a0, a1, a0, 12 +; RV32IMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12 ; RV32IMXQCIAC-NEXT: ret ; ; RV32IZBAMXQCIAC-LABEL: shladdc1equalc2: ; RV32IZBAMXQCIAC: # %bb.0: # %entry ; RV32IZBAMXQCIAC-NEXT: slli a1, a1, 12 -; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a1, a0, 12 +; RV32IZBAMXQCIAC-NEXT: qc.shladd a0, a0, a1, 12 ; RV32IZBAMXQCIAC-NEXT: ret entry: %shlc1 = shl nsw i32 %a, 12 `````````` </details> https://github.com/llvm/llvm-project/pull/149770 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
