[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

Vikram Hegde via llvm-branch-commits Tue, 15 Jul 2025 03:05:24 -0700

https://github.com/vikramRH updated 
https://github.com/llvm/llvm-project/pull/148115


>From 17afb0ff6329cb1cf676c5add1c1a3818ce96e11 Mon Sep 17 00:00:00 2001
From: vikhegde <vikram.he...@amd.com>
Date: Thu, 10 Jul 2025 18:53:39 +0530
Subject: [PATCH] [AMDGPU][NPM] Add isRequired to passes missing it

---
 llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h   | 1 +
 llvm/include/llvm/Transforms/Utils/LoopSimplify.h      | 1 +
 llvm/lib/Target/AMDGPU/AMDGPU.h                        | 3 +++
 llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h            | 1 +
 llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h | 1 +
 llvm/lib/Target/AMDGPU/GCNNSAReassign.h                | 1 +
 llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h         | 1 +
 llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h      | 1 +
 llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h               | 1 +
 llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h               | 1 +
 llvm/lib/Target/AMDGPU/SILowerControlFlow.h            | 1 +
 llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h             | 1 +
 llvm/lib/Target/AMDGPU/SILowerWWMCopies.h              | 1 +
 llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h          | 1 +
 llvm/lib/Target/AMDGPU/SIWholeQuadMode.h               | 1 +
 llvm/test/Feature/optnone-opt.ll                       | 1 -
 16 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h 
b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
index f68067d935458..f50511c9c0972 100644
--- a/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
+++ b/llvm/include/llvm/Transforms/Scalar/StructurizeCFG.h
@@ -23,6 +23,7 @@ struct StructurizeCFGPass : PassInfoMixin<StructurizeCFGPass> 
{
                      function_ref<StringRef(StringRef)> MapClassName2PassName);
 
   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h 
b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
index 8f3fa1f2b18ef..d179002fd6a27 100644
--- a/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
+++ b/llvm/include/llvm/Transforms/Utils/LoopSimplify.h
@@ -54,6 +54,7 @@ class ScalarEvolution;
 class LoopSimplifyPass : public PassInfoMixin<LoopSimplifyPass> {
 public:
   LLVM_ABI PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+  static bool isRequired() { return true; }
 };
 
 /// Simplify each loop in a loop nest recursively.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.h b/llvm/lib/Target/AMDGPU/AMDGPU.h
index 23f106a9c1d4d..4a19fe3df6fd9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.h
@@ -90,6 +90,7 @@ class SILowerI1CopiesPass : public 
PassInfoMixin<SILowerI1CopiesPass> {
   SILowerI1CopiesPass() = default;
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 
 void initializeAMDGPUDAGToDAGISelLegacyPass(PassRegistry &);
@@ -365,6 +366,7 @@ class SIModeRegisterPass : public 
PassInfoMixin<SIModeRegisterPass> {
 public:
   SIModeRegisterPass() {}
   PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager 
&AM);
+  static bool isRequired() { return true; }
 };
 
 class SIMemoryLegalizerPass : public PassInfoMixin<SIMemoryLegalizerPass> {
@@ -477,6 +479,7 @@ class SIAnnotateControlFlowPass
 public:
   SIAnnotateControlFlowPass(const AMDGPUTargetMachine &TM) : TM(TM) {}
   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+  static bool isRequired() { return true; }
 };
 
 void initializeSIAnnotateControlFlowLegacyPass(PassRegistry &);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h 
b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index f3b9364fdb92b..db5a1c0ac71aa 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -287,6 +287,7 @@ class AMDGPUISelDAGToDAGPass : public SelectionDAGISelPass {
 
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 
 class AMDGPUDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h 
b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
index 2fd98a2ee1a93..d6fb0e53e1169 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUUnifyDivergentExitNodes.h
@@ -29,6 +29,7 @@ class AMDGPUUnifyDivergentExitNodesPass
     : public PassInfoMixin<AMDGPUUnifyDivergentExitNodesPass> {
 public:
   PreservedAnalyses run(Function &F, FunctionAnalysisManager &AM);
+  static bool isRequired() { return true; }
 };
 
 } // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h 
b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
index 97a72e7ddbb24..4f2abe0dd0086 100644
--- a/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
+++ b/llvm/lib/Target/AMDGPU/GCNNSAReassign.h
@@ -16,6 +16,7 @@ class GCNNSAReassignPass : public 
PassInfoMixin<GCNNSAReassignPass> {
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h 
b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
index 4cd7dea83a061..4c4ac344cb206 100644
--- a/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
+++ b/llvm/lib/Target/AMDGPU/GCNPreRALongBranchReg.h
@@ -17,6 +17,7 @@ class GCNPreRALongBranchRegPass
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h 
b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
index b2c3190b5c6ba..4e97128bdc2d5 100644
--- a/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
+++ b/llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.h
@@ -17,6 +17,7 @@ class GCNRewritePartialRegUsesPass
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h 
b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
index d7551a45887b9..12b87d756e664 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.h
@@ -18,6 +18,7 @@ class SIFixSGPRCopiesPass : public 
PassInfoMixin<SIFixSGPRCopiesPass> {
   SIFixSGPRCopiesPass() = default;
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 
 } // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h 
b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
index 7b098b71597ff..0637b5d1750f9 100644
--- a/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
+++ b/llvm/lib/Target/AMDGPU/SIFixVGPRCopies.h
@@ -16,6 +16,7 @@ class SIFixVGPRCopiesPass : public 
PassInfoMixin<SIFixVGPRCopiesPass> {
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h 
b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
index 23803c679c246..478558dfbf97f 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.h
@@ -16,6 +16,7 @@ class SILowerControlFlowPass : public 
PassInfoMixin<SILowerControlFlowPass> {
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h 
b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
index 64ba3029f1c55..cfc25bba764e9 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.h
@@ -21,6 +21,7 @@ class SILowerSGPRSpillsPass : public 
PassInfoMixin<SILowerSGPRSpillsPass> {
     // SILowerSGPRSpills introduces new Virtual VGPRs for spilling SGPRs.
     return MachineFunctionProperties().setIsSSA().setNoVRegs();
   }
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h 
b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
index cfc8100901760..5c17a479d953c 100644
--- a/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
+++ b/llvm/lib/Target/AMDGPU/SILowerWWMCopies.h
@@ -16,6 +16,7 @@ class SILowerWWMCopiesPass : public 
PassInfoMixin<SILowerWWMCopiesPass> {
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h 
b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
index 9964817649168..6eae4756d59b2 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.h
@@ -18,6 +18,7 @@ class SIPreAllocateWWMRegsPass
 public:
   PreservedAnalyses run(MachineFunction &MF,
                         MachineFunctionAnalysisManager &MFAM);
+  static bool isRequired() { return true; }
 };
 
 } // namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h 
b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
index 87350b810bba7..b49a0fc3f6a4d 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.h
@@ -20,6 +20,7 @@ class SIWholeQuadModePass : public 
PassInfoMixin<SIWholeQuadModePass> {
   MachineFunctionProperties getClearedProperties() const {
     return MachineFunctionProperties().setIsSSA();
   }
+  static bool isRequired() { return true; }
 };
 } // namespace llvm
 
diff --git a/llvm/test/Feature/optnone-opt.ll b/llvm/test/Feature/optnone-opt.ll
index 83ff946320f53..795c9bd544463 100644
--- a/llvm/test/Feature/optnone-opt.ll
+++ b/llvm/test/Feature/optnone-opt.ll
@@ -54,7 +54,6 @@ attributes #0 = { optnone noinline }
 ; Loop IR passes that opt doesn't turn on by default.
 ; LoopPassManager should not be skipped over an optnone function
 ; NPM-LOOP-NOT: Skipping pass: PassManager
-; NPM-LOOP-DAG: Skipping pass: LoopSimplifyPass on foo
 ; NPM-LOOP-DAG: Skipping pass: LCSSAPass
 ; NPM-LOOP-DAG: Skipping pass: IndVarSimplifyPass
 ; NPM-LOOP-DAG: Skipping pass: SimpleLoopUnswitchPass

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[llvm-branch-commits] [llvm] [AMDGPU][NPM] Add isRequired to passes missing it (PR #148115)

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