Author: Jim Lin Date: 2025-07-04T14:36:18+08:00 New Revision: f724d31a37ee9d15d91c38b9e2fa7dba81db6155
URL: https://github.com/llvm/llvm-project/commit/f724d31a37ee9d15d91c38b9e2fa7dba81db6155 DIFF: https://github.com/llvm/llvm-project/commit/f724d31a37ee9d15d91c38b9e2fa7dba81db6155.diff LOG: [RISCV] Trim line to 80 chars in RISCVInstrInfoXAndes.td. NFC. Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td index 6954a955af6e2..f2a1866510ded 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXAndes.td @@ -69,7 +69,8 @@ def Log2 : SDNodeXForm<imm, [{ //===----------------------------------------------------------------------===// class NDSRVInstBB<bit cs, string opcodestr> - : RVInst<(outs), (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10), + : RVInst<(outs), + (ins GPR:$rs1, uimmlog2xlen:$cimm, bare_simm11_lsb0:$imm10), opcodestr, "$rs1, $cimm, $imm10", [], InstFormatNDS_BRANCH_10>, Sched<[WriteJmp, ReadIALU]> { bits<10> imm10; @@ -117,7 +118,8 @@ class NDSRVInstBC<bits<3> funct3, string opcodestr> } class NDSRVInstBFO<bits<3> funct3, string opcodestr> - : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), + : RVInst<(outs GPR:$rd), + (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), opcodestr, "$rd, $rs1, $msb, $lsb", [], InstFormatOther>, Sched<[WriteIALU, ReadIALU]> { bits<5> rd; @@ -409,7 +411,8 @@ multiclass VPseudoVNCVT_BF16_S { defvar constraint = "@earlyclobber $rd"; foreach m = MxListFW in { let VLMul = m.value, SEW=16 in - def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass, constraint>, + def "_" # m.MX : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.wvrclass, + constraint>, SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX, 16, forcePassthruRead=true>; } @@ -420,8 +423,10 @@ multiclass VPatConversionS_BF16<string intrinsic, string instruction> { defvar fvti = fvtiToFWti.Vti; defvar fwti = fvtiToFWti.Wti; let Predicates = [HasVendorXAndesVBFHCvt] in - def : VPatUnaryNoMask<intrinsic, instruction, "BF16", fwti.Vector, fvti.Vector, - fvti.Log2SEW, fvti.LMul, fwti.RegClass, fvti.RegClass>; + def : VPatUnaryNoMask<intrinsic, instruction, "BF16", + fwti.Vector, fvti.Vector, + fvti.Log2SEW, fvti.LMul, + fwti.RegClass, fvti.RegClass>; } } @@ -430,8 +435,10 @@ multiclass VPatConversionBF16_S<string intrinsic, string instruction> { defvar fvti = fvtiToFWti.Vti; defvar fwti = fvtiToFWti.Wti; let Predicates = [HasVendorXAndesVBFHCvt] in - def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S", fvti.Vector, fwti.Vector, - fvti.Log2SEW, fvti.LMul, fvti.RegClass, fwti.RegClass>; + def : VPatUnaryNoMaskRoundingMode<intrinsic, instruction, "S", + fvti.Vector, fwti.Vector, + fvti.Log2SEW, fvti.LMul, + fvti.RegClass, fwti.RegClass>; } } @@ -451,7 +458,8 @@ multiclass VPatVFPMADBinaryV_VX_RM<string intrinsic, string instruction, list<VTypeInfo> vtilist> { foreach vti = vtilist in { defvar kind = "V"#vti.ScalarSuffix; - defm : VPatBinaryRoundingMode<intrinsic, instruction#"_"#kind#"_"#vti.LMul.MX, + defm : VPatBinaryRoundingMode<intrinsic, + instruction#"_"#kind#"_"#vti.LMul.MX, vti.Vector, vti.Vector, f32, vti.Mask, vti.Log2SEW, vti.RegClass, vti.RegClass, FPR32>; @@ -639,8 +647,10 @@ defm PseudoNDS_VFWCVT_S_BF16 : VPseudoVWCVT_S_BF16; defm PseudoNDS_VFNCVT_BF16_S : VPseudoVNCVT_BF16_S; } // Predicates = [HasVendorXAndesVBFHCvt] -defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16", "PseudoNDS_VFWCVT_S">; -defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s", "PseudoNDS_VFNCVT_BF16">; +defm : VPatConversionS_BF16<"int_riscv_nds_vfwcvt_s_bf16", + "PseudoNDS_VFWCVT_S">; +defm : VPatConversionBF16_S<"int_riscv_nds_vfncvt_bf16_s", + "PseudoNDS_VFNCVT_BF16">; let Predicates = [HasVendorXAndesVPackFPH], mayRaiseFPException = true in { @@ -648,8 +658,10 @@ defm PseudoNDS_VFPMADT : VPseudoVFPMAD_VF_RM; defm PseudoNDS_VFPMADB : VPseudoVFPMAD_VF_RM; } // Predicates = [HasVendorXAndesVPackFPH] -defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT", AllFP16Vectors>; -defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB", AllFP16Vectors>; +defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadt", "PseudoNDS_VFPMADT", + AllFP16Vectors>; +defm : VPatVFPMADBinaryV_VX_RM<"int_riscv_nds_vfpmadb", "PseudoNDS_VFPMADB", + AllFP16Vectors>; let Predicates = [HasVendorXAndesVDot] in { defm PseudoNDS_VD4DOTS : VPseudoVD4DOT_VV; @@ -669,9 +681,12 @@ defset list<VTypeInfoToWide> AllQuadWidenableVD4DOTVectors = { def : VTypeInfoToWide<VI16M8, VI64M8>; } -defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS", AllQuadWidenableVD4DOTVectors>; -defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU", AllQuadWidenableVD4DOTVectors>; -defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", AllQuadWidenableVD4DOTVectors>; +defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dots", "PseudoNDS_VD4DOTS", + AllQuadWidenableVD4DOTVectors>; +defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotu", "PseudoNDS_VD4DOTU", + AllQuadWidenableVD4DOTVectors>; +defm : VPatTernaryVD4DOT_VV<"int_riscv_nds_vd4dotsu", "PseudoNDS_VD4DOTSU", + AllQuadWidenableVD4DOTVectors>; //===----------------------------------------------------------------------===// // Pseudo-instructions for SFB (Short Forward Branch) @@ -681,12 +696,14 @@ let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { def PseudoCCNDS_BFOS : Pseudo<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>, + GPR:$falsev, GPR:$rs1, + uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; def PseudoCCNDS_BFOZ : Pseudo<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>, + GPR:$falsev, GPR:$rs1, + uimmlog2xlen:$msb, uimmlog2xlen:$lsb), []>, Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, ReadSFBALU]>; } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
