https://github.com/arsenm updated
https://github.com/llvm/llvm-project/pull/128469
>From 4e83e255ae747198877c0b5534a4656bca4b4b1d Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Sun, 23 Feb 2025 11:21:34 +0700
Subject: [PATCH 1/2] RegAlloc: Use new approach to handling failed allocations
This fixes an assert after allocation failure.
Rather than collecting failed virtual registers and hacking
on the uses after the fact, directly hack on the uses and rewrite
the registers to the dummy assignment immediately.
Previously we were bypassing LiveRegMatrix and directly assigning
in the VirtRegMap. This resulted in inconsistencies where illegal
overlapping assignments were missing. Rather than try to hack in
some system to manage these in LiveRegMatrix (i.e. hacking around
cases with invalid iterators), avoid this by directly using the
physreg. This should also allow removal of special casing in
virtregrewriter for failed allocations.
---
llvm/lib/CodeGen/RegAllocBase.cpp | 66 ++++++-------------
llvm/lib/CodeGen/RegAllocBase.h | 3 +-
llvm/lib/CodeGen/RegAllocBasic.cpp | 1 -
llvm/lib/CodeGen/RegAllocGreedy.cpp | 1 -
llvm/lib/CodeGen/VirtRegMap.cpp | 3 +-
...e-registers-assertion-after-ra-failure.ll} | 7 +-
.../AMDGPU/illegal-eviction-assert.mir | 4 +-
...-reg-class-snippet-copy-use-after-free.mir | 16 ++---
llvm/test/CodeGen/AMDGPU/issue48473.mir | 2 +-
...ster-killed-error-after-alloc-failure0.mir | 18 ++---
10 files changed, 47 insertions(+), 74 deletions(-)
rename
llvm/test/CodeGen/AMDGPU/{agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
=> agpr-copy-no-free-registers-assertion-after-ra-failure.ll} (75%)
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index d66d396a15018..b9599e77fbf0a 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -128,8 +128,7 @@ void RegAllocBase::allocatePhysRegs() {
AvailablePhysReg = getErrorAssignment(*RC, MI);
// Keep going after reporting the error.
- VRM->assignVirt2Phys(VirtReg->reg(), AvailablePhysReg);
- FailedVRegs.insert(VirtReg->reg());
+ cleanupFailedVReg(VirtReg->reg(), AvailablePhysReg, SplitVRegs);
} else if (AvailablePhysReg)
Matrix->assign(*VirtReg, AvailablePhysReg);
@@ -163,58 +162,35 @@ void RegAllocBase::postOptimization() {
DeadRemats.clear();
}
-void RegAllocBase::cleanupFailedVRegs() {
- SmallSet<Register, 8> JunkRegs;
-
- for (Register FailedReg : FailedVRegs) {
- JunkRegs.insert(FailedReg);
-
- MCRegister PhysReg = VRM->getPhys(FailedReg);
- LiveInterval &FailedInterval = LIS->getInterval(FailedReg);
-
- // The liveness information for the failed register and anything
interfering
- // with the physical register we arbitrarily chose is junk and needs to be
- // deleted.
- for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
- LiveIntervalUnion::Query &Q = Matrix->query(FailedInterval, *Units);
- for (const LiveInterval *InterferingReg : Q.interferingVRegs())
- JunkRegs.insert(InterferingReg->reg());
- LIS->removeRegUnit(*Units);
- }
+void RegAllocBase::cleanupFailedVReg(Register FailedReg, MCRegister PhysReg,
+ SmallVectorImpl<Register> &SplitRegs) {
+ // We still should produce valid IR. Kill all the uses and reduce the live
+ // ranges so that we don't think it's possible to introduce kill flags later
+ // which will fail the verifier.
+ for (MachineOperand &MO : MRI->reg_operands(FailedReg)) {
+ if (MO.readsReg())
+ MO.setIsUndef(true);
}
- for (Register JunkReg : JunkRegs) {
- MCRegister PhysReg = VRM->getPhys(JunkReg);
- // We still should produce valid IR. Kill all the uses and reduce the live
- // ranges so that we don't think it's possible to introduce kill flags
- // later which will fail the verifier.
- for (MachineOperand &MO : MRI->reg_operands(JunkReg)) {
- if (MO.readsReg())
- MO.setIsUndef(true);
- }
-
- // The liveness of the assigned physical register is also now unreliable.
+ if (!MRI->isReserved(PhysReg)) {
+ // Physical liveness for any aliasing registers is now unreliable, so
delete
+ // the uses.
for (MCRegAliasIterator Aliases(PhysReg, TRI, true); Aliases.isValid();
++Aliases) {
for (MachineOperand &MO : MRI->reg_operands(*Aliases)) {
- if (MO.readsReg())
+ if (MO.readsReg()) {
MO.setIsUndef(true);
- }
- }
-
- LiveInterval &JunkLI = LIS->getInterval(JunkReg);
- if (LIS->shrinkToUses(&JunkLI)) {
- SmallVector<LiveInterval *, 8> SplitLIs;
- LIS->splitSeparateComponents(JunkLI, SplitLIs);
-
- VRM->grow();
- Register Original = VRM->getOriginal(JunkReg);
- for (LiveInterval *SplitLI : SplitLIs) {
- VRM->setIsSplitFromReg(SplitLI->reg(), Original);
- VRM->assignVirt2Phys(SplitLI->reg(), PhysReg);
+ LIS->removeAllRegUnitsForPhysReg(MO.getReg());
+ }
}
}
}
+
+ // Directly perform the rewrite, and do not leave it to VirtRegRewriter as
+ // usual. This avoids trying to manage illegal overlapping assignments in
+ // LiveRegMatrix.
+ MRI->replaceRegWith(FailedReg, PhysReg);
+ LIS->removeInterval(FailedReg);
}
void RegAllocBase::enqueue(const LiveInterval *LI) {
diff --git a/llvm/lib/CodeGen/RegAllocBase.h b/llvm/lib/CodeGen/RegAllocBase.h
index 1fdbab694bb0e..f1b5af8cd4d74 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/lib/CodeGen/RegAllocBase.h
@@ -108,7 +108,8 @@ class RegAllocBase {
/// Perform cleanups on registers that failed to allocate. This hacks on the
/// liveness in order to avoid spurious verifier errors in later passes.
- void cleanupFailedVRegs();
+ void cleanupFailedVReg(Register FailedVReg, MCRegister PhysReg,
+ SmallVectorImpl<Register> &SplitRegs);
// Get a temporary reference to a Spiller instance.
virtual Spiller &spiller() = 0;
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp
b/llvm/lib/CodeGen/RegAllocBasic.cpp
index d240bf916ac05..51e047b2fa3f0 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -329,7 +329,6 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
allocatePhysRegs();
postOptimization();
- cleanupFailedVRegs();
// Diagnostic output before rewriting
LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n");
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index f8faf766d9ec5..6dba1bd8f47dd 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -2927,7 +2927,6 @@ bool RAGreedy::run(MachineFunction &mf) {
if (VerifyEnabled)
MF->verify(LIS, Indexes, "Before post optimization", &errs());
postOptimization();
- cleanupFailedVRegs();
reportStats();
releaseMemory();
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 4e4c89eba7aa9..81a82e898a901 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -620,8 +620,7 @@ void VirtRegRewriter::rewrite() {
assert(Register(PhysReg).isPhysical());
RewriteRegs.insert(PhysReg);
- assert((!MRI->isReserved(PhysReg) || !IsValidAlloc) &&
- "Reserved register assignment");
+ assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
// Preserve semantics of sub-register operands.
unsigned SubReg = MO.getSubReg();
diff --git
a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
similarity index 75%
rename from
llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
rename to
llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
index 5f2e9af378f08..f3eb7a42cb823 100644
---
a/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.xfail.ll
+++
b/llvm/test/CodeGen/AMDGPU/agpr-copy-no-free-registers-assertion-after-ra-failure.ll
@@ -1,8 +1,7 @@
-; REQUIRES: asserts
-; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=null
%s 2>&1 | FileCheck -check-prefix=CRASH %s
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -filetype=null %s 2>&1
| FileCheck -check-prefix=ERR %s
+; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -vgpr-regalloc=basic
-filetype=null %s 2>&1 | FileCheck -check-prefix=ERR %s
-; CRASH: error: <unknown>:0:0: no registers from class available to allocate
in function 'no_free_vgprs_at_agpr_to_agpr_copy'
-; CRASH: Cannot access invalid iterator
+; ERR: error: <unknown>:0:0: no registers from class available to allocate in
function 'no_free_vgprs_at_agpr_to_agpr_copy'
define void @no_free_vgprs_at_agpr_to_agpr_copy(float %v0, float %v1) #0 {
%asm = call { <32 x i32>, <16 x float> } asm sideeffect "; def $0 $1",
"=${v[0:31]},=${a[0:15]}"()
diff --git a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
index e583b168c15f7..e32fa90ead4f4 100644
--- a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
+++ b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
@@ -17,8 +17,8 @@
...
-# CHECK: S_NOP 0, implicit-def
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit-def $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27,
implicit-def dead $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def
$vgpr28_vgpr29_vgpr30_vgpr31, implicit-def dead $vgpr0_vgpr1_vgpr2_vgpr3
-# CHECK: S_NOP 0, implicit killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit killed undef
$vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3, implicit killed undef $vgpr28_vgpr29_vgpr30_vgpr31,
implicit undef $vgpr0_vgpr1_vgpr2_vgpr3
+# CHECK: S_NOP 0, implicit-def
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit-def $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27,
implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def
$vgpr28_vgpr29_vgpr30_vgpr31, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
+# CHECK: S_NOP 0, implicit killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit killed undef
$vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3, implicit killed undef $vgpr28_vgpr29_vgpr30_vgpr31,
implicit killed undef $vgpr0_vgpr1_vgpr2_vgpr3
---
name: foo
diff --git
a/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
b/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
index 6d63a4a1cc0ab..c1e0d0716acae 100644
---
a/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
+++
b/llvm/test/CodeGen/AMDGPU/inflated-reg-class-snippet-copy-use-after-free.mir
@@ -27,10 +27,10 @@
# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free
# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub3
# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit
$exec :: (store (s512) into %stack.0, align 4, addrspace 5)
-# CHECK-NEXT: dead [[RESTORE0:%[0-9]+]]:vreg_512_align2 =
SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from
%stack.0, align 4, addrspace 5)
-# CHECK-NEXT: dead early-clobber [[MFMA0:%[0-9]+]]:vreg_512_align2 =
V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32, undef
[[RESTORE0]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit
$exec
-# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef
[[MFMA0]].sub2_sub3 {
-# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef
[[MFMA0]].sub0
+# CHECK-NEXT: [[RESTORE0:%[0-9]+]]:vreg_512_align2 = SI_SPILL_V512_RESTORE
%stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4,
addrspace 5)
+# CHECK-NEXT: early-clobber
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
= V_MFMA_F32_16X16X1F32_vgprcd_e64 undef %3:vgpr_32, undef %3:vgpr_32,
[[RESTORE0]], 0, 0, 0, implicit $mode, implicit $exec, implicit $mode, implicit
$exec
+# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef
$vgpr2_vgpr3 {
+# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr0
# CHECK-NEXT: }
# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY
[[SPLIT0]].sub2_sub3 {
# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0
@@ -118,10 +118,10 @@ body: |
# CHECK-LABEL: name: inflated_reg_class_copy_use_after_free_lane_subset
# CHECK: S_NOP 0, implicit-def [[ORIG_REG:%[0-9]+]].sub0_sub1_sub2_sub3
# CHECK-NEXT: SI_SPILL_AV512_SAVE [[ORIG_REG]], %stack.0, $sgpr32, 0, implicit
$exec :: (store (s512) into %stack.0, align 4, addrspace 5)
-# CHECK-NEXT: dead [[RESTORE_0:%[0-9]+]]:av_512_align2 =
SI_SPILL_AV512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512)
from %stack.0, align 4, addrspace 5)
-# CHECK-NEXT: S_NOP 0, implicit-def dead early-clobber [[REG1:%[0-9]+]],
implicit undef [[RESTORE_0]].sub0_sub1_sub2_sub3, implicit undef
[[RESTORE_0]].sub4_sub5_sub6_sub7
-# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef
[[REG1]].sub2_sub3 {
-# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef [[REG1]].sub0
+# CHECK-NEXT: [[RESTORE_0:%[0-9]+]]:av_512_align2 = SI_SPILL_AV512_RESTORE
%stack.0, $sgpr32, 0, implicit $exec :: (load (s512) from %stack.0, align 4,
addrspace 5)
+# CHECK-NEXT: S_NOP 0, implicit-def early-clobber
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
implicit [[RESTORE_0]].sub0_sub1_sub2_sub3, implicit
[[RESTORE_0]].sub4_sub5_sub6_sub7
+# CHECK-NEXT: undef [[SPLIT0:%[0-9]+]].sub2_sub3:av_512_align2 = COPY undef
$vgpr2_vgpr3 {
+# CHECK-NEXT: internal [[SPLIT0]].sub0:av_512_align2 = COPY undef $vgpr0
# CHECK-NEXT: }
# CHECK-NEXT: undef [[SPLIT1:%[0-9]+]].sub2_sub3:av_512_align2 = COPY
[[SPLIT0]].sub2_sub3 {
# CHECK-NEXT: internal [[SPLIT1]].sub0:av_512_align2 = COPY [[SPLIT0]].sub0
diff --git a/llvm/test/CodeGen/AMDGPU/issue48473.mir
b/llvm/test/CodeGen/AMDGPU/issue48473.mir
index c5cb1445adca0..507b299e79a86 100644
--- a/llvm/test/CodeGen/AMDGPU/issue48473.mir
+++ b/llvm/test/CodeGen/AMDGPU/issue48473.mir
@@ -43,7 +43,7 @@
# %25 to $sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
# CHECK-LABEL: name: issue48473
-# CHECK: S_NOP 0, implicit undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed
undef $sgpr12_sgpr13_sgpr14_sgpr15, implicit killed undef
$sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit killed undef
$sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit killed undef
$sgpr84_sgpr85_sgpr86_sgpr87, implicit killed undef
$sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, implicit killed undef
$sgpr4_sgpr5_sgpr6_sgpr7, implicit killed undef
$sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, implicit killed undef
$sgpr88_sgpr89_sgpr90_sgpr91, implicit killed undef
$sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83, implicit undef
$sgpr0_sgpr1_sgpr2_sgpr3, implicit killed undef
$sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59, implicit killed undef
$sgpr92_sgpr93_sgpr94_sgpr95, implicit killed undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit killed undef
$sgpr96_sgpr97_sgpr98_sgpr99, implicit killed undef $sgpr8_sgpr9_sgpr10_sgpr11,
implicit killed undef $sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
+# CHECK: S_NOP 0, implicit killed undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit
killed undef $sgpr12_sgpr13_sgpr14_sgpr15, implicit killed undef
$sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit killed undef
$sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit killed undef
$sgpr84_sgpr85_sgpr86_sgpr87, implicit killed undef
$sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, implicit killed undef
$sgpr4_sgpr5_sgpr6_sgpr7, implicit killed undef
$sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, implicit killed undef
$sgpr88_sgpr89_sgpr90_sgpr91, implicit killed undef
$sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83, implicit undef
$sgpr0_sgpr1_sgpr2_sgpr3, implicit killed undef
$sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59, implicit killed undef
$sgpr92_sgpr93_sgpr94_sgpr95, implicit killed undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit killed undef
$sgpr96_sgpr97_sgpr98_sgpr99, implicit killed undef $sgpr8_sgpr9_sgpr10_sgpr11,
implicit killed undef $sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
---
name: issue48473
diff --git
a/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
b/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
index e2a839ea9d24e..306788b0bf5ed 100644
--- a/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
+++ b/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
@@ -14,23 +14,23 @@
# ERR: error: <unknown>:0:0: ran out of registers during register allocation
# GREEDY: SI_SPILL_V256_SAVE undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-# GREEDY-NEXT: SI_SPILL_V512_SAVE undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
-# GREEDY-NEXT: SI_SPILL_V128_SAVE undef $vgpr0_vgpr1_vgpr2_vgpr3
+# GREEDY-NEXT: SI_SPILL_V512_SAVE killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
%stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4,
addrspace 5)
+# GREEDY-NEXT: SI_SPILL_V128_SAVE killed undef $vgpr0_vgpr1_vgpr2_vgpr3
-# GREEDY: dead
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
= SI_SPILL_V512_RESTORE
-# GREEDY: dead $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 =
SI_SPILL_V256_RESTORE
-# GREEDY: S_NOP 0, implicit undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit
undef $vgpr0_vgpr1_vgpr2_vgpr3
+# GREEDY:
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
= SI_SPILL_V512_RESTORE
+# GREEDY: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 =
SI_SPILL_V256_RESTORE
+# GREEDY: S_NOP 0, implicit killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit
killed undef $vgpr0_vgpr1_vgpr2_vgpr3
# GREEDY: S_NOP 0, implicit killed undef $vgpr20_vgpr21
# BASIC: SI_SPILL_V128_SAVE undef $vgpr0_vgpr1_vgpr2_vgpr3
# BASIC: SI_SPILL_V256_SAVE killed undef
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
-# BASIC: SI_SPILL_V512_SAVE undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
+# BASIC: SI_SPILL_V512_SAVE killed undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
%stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4,
addrspace 5)
# BASIC: SI_SPILL_V64_SAVE killed undef $vgpr0_vgpr1, %stack.{{[0-9]+}},
$sgpr32, 0, implicit $exec :: (store (s64) into %stack.{{[0-9]+}}, align 4,
addrspace 5)
-# BASIC: dead
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
= SI_SPILL_V512_RESTORE
+# BASIC:
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
= SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512)
from %stack.0, align 4, addrspace 5)
# BASIC: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 =
SI_SPILL_V256_RESTORE
-# BASIC: dead $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE
-# BASIC: S_NOP 0, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
implicit killed undef
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3
+# BASIC: $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE
+# BASIC: S_NOP 0, implicit killed undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
implicit killed undef
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3
# BASIC: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE
--- |
>From 6af25a4e2bc6a872f31f833fdabc14712544a649 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <matthew.arsena...@amd.com>
Date: Mon, 24 Feb 2025 14:48:32 +0700
Subject: [PATCH 2/2] Remove special casing in VirtRegRewriter
We could now delete FailedRegAlloc since the special case
handling is now local to the allocation passes. We're still using
it to avoid repeated errors, so that would need some new local state.
---
llvm/lib/CodeGen/VirtRegMap.cpp | 16 ++--------------
.../CodeGen/AMDGPU/illegal-eviction-assert.mir | 4 ++--
llvm/test/CodeGen/AMDGPU/issue48473.mir | 2 +-
...egister-killed-error-after-alloc-failure0.mir | 16 ++++++++--------
4 files changed, 13 insertions(+), 25 deletions(-)
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index 81a82e898a901..0fc3e5d9a3052 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -88,9 +88,7 @@ void VirtRegMap::assignVirt2Phys(Register virtReg, MCRegister
physReg) {
assert(!Virt2PhysMap[virtReg] &&
"attempt to assign physical register to already mapped "
"virtual register");
- assert((!getRegInfo().isReserved(physReg) ||
- MF->getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedRegAlloc)) &&
+ assert(!getRegInfo().isReserved(physReg) &&
"Attempt to map virtReg to a reserved physReg");
Virt2PhysMap[virtReg] = physReg;
}
@@ -598,9 +596,6 @@ void VirtRegRewriter::rewrite() {
SmallVector<Register, 8> SuperDefs;
SmallVector<Register, 8> SuperKills;
- const bool IsValidAlloc = !MF->getProperties().hasProperty(
- MachineFunctionProperties::Property::FailedRegAlloc);
-
for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
MBBI != MBBE; ++MBBI) {
LLVM_DEBUG(MBBI->print(dbgs(), Indexes));
@@ -695,14 +690,7 @@ void VirtRegRewriter::rewrite() {
// Rewrite. Note we could have used MachineOperand::substPhysReg(), but
// we need the inlining here.
MO.setReg(PhysReg);
-
- // Defend against generating invalid flags in allocation failure
- // scenarios. We have have assigned a register which was undefined, or
a
- // reserved register which cannot be renamable.
- if (LLVM_LIKELY(IsValidAlloc))
- MO.setIsRenamable(true);
- else if (MO.isUse())
- MO.setIsUndef(true);
+ MO.setIsRenamable(true);
}
// Add any missing super-register kills after rewriting the whole
diff --git a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
index e32fa90ead4f4..ca2c8928bbc39 100644
--- a/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
+++ b/llvm/test/CodeGen/AMDGPU/illegal-eviction-assert.mir
@@ -17,8 +17,8 @@
...
-# CHECK: S_NOP 0, implicit-def
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit-def $vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27,
implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit-def
$vgpr28_vgpr29_vgpr30_vgpr31, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3
-# CHECK: S_NOP 0, implicit killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit killed undef
$vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3, implicit killed undef $vgpr28_vgpr29_vgpr30_vgpr31,
implicit killed undef $vgpr0_vgpr1_vgpr2_vgpr3
+# CHECK: S_NOP 0, implicit-def renamable
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit-def renamable
$vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit-def
$vgpr0_vgpr1_vgpr2_vgpr3, implicit-def renamable $vgpr28_vgpr29_vgpr30_vgpr31,
implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3
+# CHECK: S_NOP 0, implicit killed renamable
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit killed renamable
$vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3, implicit killed renamable
$vgpr28_vgpr29_vgpr30_vgpr31, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3
---
name: foo
diff --git a/llvm/test/CodeGen/AMDGPU/issue48473.mir
b/llvm/test/CodeGen/AMDGPU/issue48473.mir
index 507b299e79a86..dd73e65de7cb6 100644
--- a/llvm/test/CodeGen/AMDGPU/issue48473.mir
+++ b/llvm/test/CodeGen/AMDGPU/issue48473.mir
@@ -43,7 +43,7 @@
# %25 to $sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
# CHECK-LABEL: name: issue48473
-# CHECK: S_NOP 0, implicit killed undef $sgpr0_sgpr1_sgpr2_sgpr3, implicit
killed undef $sgpr12_sgpr13_sgpr14_sgpr15, implicit killed undef
$sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit killed undef
$sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit killed undef
$sgpr84_sgpr85_sgpr86_sgpr87, implicit killed undef
$sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, implicit killed undef
$sgpr4_sgpr5_sgpr6_sgpr7, implicit killed undef
$sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, implicit killed undef
$sgpr88_sgpr89_sgpr90_sgpr91, implicit killed undef
$sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83, implicit undef
$sgpr0_sgpr1_sgpr2_sgpr3, implicit killed undef
$sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59, implicit killed undef
$sgpr92_sgpr93_sgpr94_sgpr95, implicit killed undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit undef
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit killed undef
$sgpr96_sgpr97_sgpr98_sgpr99, implicit killed undef $sgpr8_sgpr9_sgpr10_sgpr11,
implicit killed undef $sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
+# CHECK: S_NOP 0, implicit killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, implicit
killed renamable $sgpr12_sgpr13_sgpr14_sgpr15, implicit killed renamable
$sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23, implicit killed
renamable $sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31, implicit
killed renamable $sgpr84_sgpr85_sgpr86_sgpr87, implicit killed renamable
$sgpr36_sgpr37_sgpr38_sgpr39_sgpr40_sgpr41_sgpr42_sgpr43, implicit killed
renamable $sgpr4_sgpr5_sgpr6_sgpr7, implicit killed renamable
$sgpr44_sgpr45_sgpr46_sgpr47_sgpr48_sgpr49_sgpr50_sgpr51, implicit killed
renamable $sgpr88_sgpr89_sgpr90_sgpr91, implicit killed renamable
$sgpr76_sgpr77_sgpr78_sgpr79_sgpr80_sgpr81_sgpr82_sgpr83, implicit undef
$sgpr0_sgpr1_sgpr2_sgpr3, implicit killed renamable
$sgpr52_sgpr53_sgpr54_sgpr55_sgpr56_sgpr57_sgpr58_sgpr59, implicit killed
renamable $sgpr92_sgpr93_sgpr94_sgpr95, implicit killed renamable
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit renamable
$sgpr68_sgpr69_sgpr70_sgpr71_sgpr72_sgpr73_sgpr74_sgpr75, implicit killed
renamable $sgpr96_sgpr97_sgpr98_sgpr99, implicit killed renamable
$sgpr8_sgpr9_sgpr10_sgpr11, implicit killed renamable
$sgpr60_sgpr61_sgpr62_sgpr63_sgpr64_sgpr65_sgpr66_sgpr67
---
name: issue48473
diff --git
a/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
b/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
index 306788b0bf5ed..80343d4c342cd 100644
--- a/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
+++ b/llvm/test/CodeGen/AMDGPU/register-killed-error-after-alloc-failure0.mir
@@ -14,23 +14,23 @@
# ERR: error: <unknown>:0:0: ran out of registers during register allocation
# GREEDY: SI_SPILL_V256_SAVE undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
-# GREEDY-NEXT: SI_SPILL_V512_SAVE killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
%stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4,
addrspace 5)
-# GREEDY-NEXT: SI_SPILL_V128_SAVE killed undef $vgpr0_vgpr1_vgpr2_vgpr3
+# GREEDY-NEXT: SI_SPILL_V512_SAVE killed
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
%stack.1, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.1, align 4,
addrspace 5)
+# GREEDY-NEXT: SI_SPILL_V128_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3
# GREEDY:
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19
= SI_SPILL_V512_RESTORE
# GREEDY: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7 =
SI_SPILL_V256_RESTORE
-# GREEDY: S_NOP 0, implicit killed undef
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit
killed undef $vgpr0_vgpr1_vgpr2_vgpr3
-# GREEDY: S_NOP 0, implicit killed undef $vgpr20_vgpr21
+# GREEDY: S_NOP 0, implicit killed renamable
$vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19,
implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7, implicit
killed renamable $vgpr0_vgpr1_vgpr2_vgpr3
+# GREEDY: S_NOP 0, implicit killed renamable $vgpr20_vgpr21
# BASIC: SI_SPILL_V128_SAVE undef $vgpr0_vgpr1_vgpr2_vgpr3
-# BASIC: SI_SPILL_V256_SAVE killed undef
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
-# BASIC: SI_SPILL_V512_SAVE killed undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
%stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4,
addrspace 5)
-# BASIC: SI_SPILL_V64_SAVE killed undef $vgpr0_vgpr1, %stack.{{[0-9]+}},
$sgpr32, 0, implicit $exec :: (store (s64) into %stack.{{[0-9]+}}, align 4,
addrspace 5)
+# BASIC: SI_SPILL_V256_SAVE killed
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23
+# BASIC: SI_SPILL_V512_SAVE killed
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
%stack.0, $sgpr32, 0, implicit $exec :: (store (s512) into %stack.0, align 4,
addrspace 5)
+# BASIC: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.{{[0-9]+}}, $sgpr32, 0,
implicit $exec :: (store (s64) into %stack.{{[0-9]+}}, align 4, addrspace 5)
# BASIC:
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
= SI_SPILL_V512_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s512)
from %stack.0, align 4, addrspace 5)
# BASIC: $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23 =
SI_SPILL_V256_RESTORE
# BASIC: $vgpr0_vgpr1_vgpr2_vgpr3 = SI_SPILL_V128_RESTORE
-# BASIC: S_NOP 0, implicit killed undef
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
implicit killed undef
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3
+# BASIC: S_NOP 0, implicit killed renamable
$vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15,
implicit killed renamable
$vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23, implicit undef
$vgpr0_vgpr1_vgpr2_vgpr3
# BASIC: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE
--- |
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