================
@@ -1005,7 +1007,8 @@ void RegAllocFastImpl::allocVirtRegUndef(MachineOperand 
&MO) {
     MO.setSubReg(0);
   }
   MO.setReg(PhysReg);
-  MO.setIsRenamable(true);
+  if (!LRI->Error)
+    MO.setIsRenamable(true);
----------------
cdevadas wrote:

```suggestion
  MO.setIsRenamable(!LRI->Error);
```

https://github.com/llvm/llvm-project/pull/128281
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