================
@@ -2639,6 +2639,10 @@ X86TargetLowering::X86TargetLowering(const
X86TargetMachine &TM,
setOperationAction(Op, MVT::f32, Promote);
}
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32);
+ setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64);
----------------
jofrn wrote:
These will still form in from `v1f16`, `v1f32`, and `v1f64`, which don't get
translated in AtomicExpand. It is reachable during DAG to DAG translation.
After scalarization, we promote:
1. `v1f32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2`
2. `f32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2` // scalarize
3. `i32,ch = AtomicLoad<(load acquire (s32) from %ir.x)> t0, t2` // cast
You mentioned earlier that a follow-up should have AtomicExpand's
shouldCastAtomicLoadInIR return none for these; this doesn't affect these cases
here though.
https://github.com/llvm/llvm-project/pull/120386
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
