[llvm-branch-commits] [llvm] [X86] Manage atomic load of fp -> int promotion in DAG (PR #120386)

[via llvm-branch-commits]

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@@ -145,3 +145,40 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind {
   %ret = load atomic <1 x i64>, ptr %x acquire, align 8
   ret <1 x i64> %ret
 }
+
+define <1 x half> @atomic_vec1_half(ptr %x) {
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jofrn wrote:

It is already scalarized from a `v1bf16` to an `i16`. It doesn't require 
setting `setOperationPromotedToType` to lower in the same way.

https://github.com/llvm/llvm-project/pull/120386
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