================
@@ -1405,11 +1412,29 @@ bool AArch64LegalizerInfo::legalizeCustom(
return Helper.lowerAbsToCNeg(MI);
case TargetOpcode::G_ICMP:
return legalizeICMP(MI, MRI, MIRBuilder);
+ case TargetOpcode::G_BITCAST:
+ return legalizeBitcast(MI, Helper);
}
llvm_unreachable("expected switch to return");
}
+bool AArch64LegalizerInfo::legalizeBitcast(MachineInstr &MI,
+ LegalizerHelper &Helper) const {
+ assert(MI.getOpcode() == TargetOpcode::G_BITCAST && "Unexpected opcode");
+ auto [DstReg, DstTy, SrcReg, SrcTy] = MI.getFirst2RegLLTs();
+ // We're trying to handle casts from i1 vectors to scalars but reloading from
+ // stack.
+ if (!DstTy.isScalar() || !SrcTy.isVector() ||
+ SrcTy.getElementType() != LLT::scalar(1))
+ return false;
+
+ auto Load = Helper.createStackStoreLoad(SrcReg, DstTy);
----------------
arsenm wrote:
Seems awkward that we can't use the SrcOp/DstOp for LegalizerHelper functions,
would be better to directly use the dest reg
https://github.com/llvm/llvm-project/pull/121171
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