https://github.com/optimisan updated
https://github.com/llvm/llvm-project/pull/119540
>From 36d5e74a51157ad2841c79c6604813a65230d0a1 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Wed, 11 Dec 2024 08:51:55 +0000
Subject: [PATCH] [CodeGen][NewPM] Port RegAllocGreedy to NPM
---
.../llvm}/CodeGen/InterferenceCache.h | 22 +-
llvm/include/llvm/CodeGen/MachineFunction.h | 1 +
llvm/include/llvm/CodeGen/Passes.h | 2 +-
.../llvm}/CodeGen/RegAllocBase.h | 2 +-
.../llvm}/CodeGen/RegAllocGreedy.h | 80 +++++---
llvm/{lib => include/llvm}/CodeGen/SplitKit.h | 24 +--
llvm/include/llvm/InitializePasses.h | 2 +-
.../llvm/Passes/MachinePassRegistry.def | 9 +
llvm/lib/CodeGen/CodeGen.cpp | 2 +-
llvm/lib/CodeGen/InlineSpiller.cpp | 2 +-
llvm/lib/CodeGen/InterferenceCache.cpp | 2 +-
llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp | 2 +-
.../lib/CodeGen/MLRegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBase.cpp | 2 +-
llvm/lib/CodeGen/RegAllocBasic.cpp | 2 +-
llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp | 2 +-
llvm/lib/CodeGen/RegAllocGreedy.cpp | 192 ++++++++++++++----
llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp | 2 +-
llvm/lib/CodeGen/SplitKit.cpp | 2 +-
llvm/lib/Passes/PassBuilder.cpp | 1 +
20 files changed, 250 insertions(+), 105 deletions(-)
rename llvm/{lib => include/llvm}/CodeGen/InterferenceCache.h (95%)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocBase.h (99%)
rename llvm/{lib => include/llvm}/CodeGen/RegAllocGreedy.h (89%)
rename llvm/{lib => include/llvm}/CodeGen/SplitKit.h (97%)
diff --git a/llvm/lib/CodeGen/InterferenceCache.h
b/llvm/include/llvm/CodeGen/InterferenceCache.h
similarity index 95%
rename from llvm/lib/CodeGen/InterferenceCache.h
rename to llvm/include/llvm/CodeGen/InterferenceCache.h
index 2a176b4f2cf7b1..dfe82916224913 100644
--- a/llvm/lib/CodeGen/InterferenceCache.h
+++ b/llvm/include/llvm/CodeGen/InterferenceCache.h
@@ -142,7 +142,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
// Point to an entry for each physreg. The entry pointed to may not be up to
// date, and it may have been reused for a different physreg.
- unsigned char* PhysRegEntries = nullptr;
+ unsigned char *PhysRegEntries = nullptr;
size_t PhysRegEntriesCount = 0;
// Next round-robin entry to be picked.
@@ -158,9 +158,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
InterferenceCache() = default;
InterferenceCache &operator=(const InterferenceCache &other) = delete;
InterferenceCache(const InterferenceCache &other) = delete;
- ~InterferenceCache() {
- free(PhysRegEntries);
- }
+ ~InterferenceCache() { free(PhysRegEntries); }
void reinitPhysRegEntries();
@@ -194,9 +192,7 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
/// Cursor - Create a dangling cursor.
Cursor() = default;
- Cursor(const Cursor &O) {
- setEntry(O.CacheEntry);
- }
+ Cursor(const Cursor &O) { setEntry(O.CacheEntry); }
Cursor &operator=(const Cursor &O) {
setEntry(O.CacheEntry);
@@ -220,21 +216,15 @@ class LLVM_LIBRARY_VISIBILITY InterferenceCache {
}
/// hasInterference - Return true if the current block has any
interference.
- bool hasInterference() {
- return Current->First.isValid();
- }
+ bool hasInterference() { return Current->First.isValid(); }
/// first - Return the starting index of the first interfering range in the
/// current block.
- SlotIndex first() {
- return Current->First;
- }
+ SlotIndex first() { return Current->First; }
/// last - Return the ending index of the last interfering range in the
/// current block.
- SlotIndex last() {
- return Current->Last;
- }
+ SlotIndex last() { return Current->Last; }
};
};
diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h
b/llvm/include/llvm/CodeGen/MachineFunction.h
index 547cc26eda2295..ceb0fec3b6086f 100644
--- a/llvm/include/llvm/CodeGen/MachineFunction.h
+++ b/llvm/include/llvm/CodeGen/MachineFunction.h
@@ -900,6 +900,7 @@ class LLVM_ABI MachineFunction {
/// Run the current MachineFunction through the machine code verifier, useful
/// for debugger use.
+ /// TODO: Add the param LiveStks
/// \returns true if no problems were found.
bool verify(LiveIntervals *LiveInts, SlotIndexes *Indexes,
const char *Banner = nullptr, raw_ostream *OS = nullptr,
diff --git a/llvm/include/llvm/CodeGen/Passes.h
b/llvm/include/llvm/CodeGen/Passes.h
index d1fac4a304cffe..1096c34b307f9b 100644
--- a/llvm/include/llvm/CodeGen/Passes.h
+++ b/llvm/include/llvm/CodeGen/Passes.h
@@ -167,7 +167,7 @@ namespace llvm {
extern char &LiveRangeShrinkID;
/// Greedy register allocator.
- extern char &RAGreedyID;
+ extern char &RAGreedyLegacyID;
/// Basic register allocator.
extern char &RABasicID;
diff --git a/llvm/lib/CodeGen/RegAllocBase.h
b/llvm/include/llvm/CodeGen/RegAllocBase.h
similarity index 99%
rename from llvm/lib/CodeGen/RegAllocBase.h
rename to llvm/include/llvm/CodeGen/RegAllocBase.h
index a1ede08a15356d..4adfdcd866f892 100644
--- a/llvm/lib/CodeGen/RegAllocBase.h
+++ b/llvm/include/llvm/CodeGen/RegAllocBase.h
@@ -48,7 +48,7 @@ class LiveIntervals;
class LiveRegMatrix;
class MachineInstr;
class MachineRegisterInfo;
-template<typename T> class SmallVectorImpl;
+template <typename T> class SmallVectorImpl;
class Spiller;
class TargetRegisterInfo;
class VirtRegMap;
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.h
b/llvm/include/llvm/CodeGen/RegAllocGreedy.h
similarity index 89%
rename from llvm/lib/CodeGen/RegAllocGreedy.h
rename to llvm/include/llvm/CodeGen/RegAllocGreedy.h
index 89ceefd37795bc..a20d29883bd10e 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.h
+++ b/llvm/include/llvm/CodeGen/RegAllocGreedy.h
@@ -12,9 +12,6 @@
#ifndef LLVM_CODEGEN_REGALLOCGREEDY_H_
#define LLVM_CODEGEN_REGALLOCGREEDY_H_
-#include "InterferenceCache.h"
-#include "RegAllocBase.h"
-#include "SplitKit.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
@@ -22,16 +19,22 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
+#include "llvm/CodeGen/InterferenceCache.h"
#include "llvm/CodeGen/LiveDebugVariables.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
+#include "llvm/CodeGen/LiveStacks.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/RegAllocBase.h"
+#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SpillPlacement.h"
#include "llvm/CodeGen/Spiller.h"
+#include "llvm/CodeGen/SplitKit.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/PassManager.h"
#include <algorithm>
#include <cstdint>
#include <memory>
@@ -56,11 +59,30 @@ class SlotIndexes;
class TargetInstrInfo;
class VirtRegMap;
-class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
- public RegAllocBase,
+class LLVM_LIBRARY_VISIBILITY RAGreedy : public RegAllocBase,
private LiveRangeEdit::Delegate {
- // Interface to eviction advisers
public:
+ struct RequiredAnalyses {
+ VirtRegMap *VRM = nullptr;
+ LiveIntervals *LIS = nullptr;
+ LiveRegMatrix *LRM = nullptr;
+ SlotIndexes *Indexes = nullptr;
+ MachineBlockFrequencyInfo *MBFI = nullptr;
+ MachineDominatorTree *DomTree = nullptr;
+ MachineLoopInfo *Loops = nullptr;
+ MachineOptimizationRemarkEmitter *ORE = nullptr;
+ EdgeBundles *Bundles = nullptr;
+ SpillPlacement *SpillPlacer = nullptr;
+ LiveDebugVariables *DebugVars = nullptr;
+
+ // Used by InlineSpiller
+ LiveStacks *LSS;
+ // Proxies for eviction and priority advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider;
+ RegAllocPriorityAdvisorProvider *PriorityProvider;
+ };
+
+ // Interface to eviction advisers
/// Track allocation stage and eviction loop prevention during allocation.
class ExtraRegInfo final {
// RegInfo - Keep additional information about each live range.
@@ -178,6 +200,10 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
EdgeBundles *Bundles = nullptr;
SpillPlacement *SpillPlacer = nullptr;
LiveDebugVariables *DebugVars = nullptr;
+ LiveStacks *LSS = nullptr; // Used by InlineSpiller
+ // Proxy for the advisors
+ RegAllocEvictionAdvisorProvider *EvictProvider = nullptr;
+ RegAllocPriorityAdvisorProvider *PriorityProvider = nullptr;
// state
std::unique_ptr<Spiller> SpillerInstance;
@@ -282,13 +308,11 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
public:
RAGreedy(const RegAllocFilterFunc F = nullptr);
+ // Evict and priority advisors use this object, so we can construct those
+ // first and pass them here.
+ // Not required once legacy PM is removed.
+ void setAnalyses(RequiredAnalyses &Analyses);
- /// Return the pass name.
- StringRef getPassName() const override { return "Greedy Register Allocator";
}
-
- /// RAGreedy analysis usage.
- void getAnalysisUsage(AnalysisUsage &AU) const override;
- void releaseMemory() override;
Spiller &spiller() override { return *SpillerInstance; }
void enqueueImpl(const LiveInterval *LI) override;
const LiveInterval *dequeue() override;
@@ -297,19 +321,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
void aboutToRemoveInterval(const LiveInterval &) override;
/// Perform register allocation.
- bool runOnMachineFunction(MachineFunction &mf) override;
-
- MachineFunctionProperties getRequiredProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::NoPHIs);
- }
-
- MachineFunctionProperties getClearedProperties() const override {
- return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::IsSSA);
- }
+ bool run(MachineFunction &mf);
- static char ID;
+ void releaseMemory();
private:
MCRegister selectOrSplitImpl(const LiveInterval &,
@@ -451,5 +465,23 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public
MachineFunctionPass,
/// Report the statistic for each loop.
void reportStats();
};
+
+class RAGreedyPass : public PassInfoMixin<RAGreedyPass> {
+ RegAllocFilterFunc Filter;
+
+public:
+ RAGreedyPass(RegAllocFilterFunc F = nullptr) : Filter(F) {}
+ PreservedAnalyses run(MachineFunction &F, MachineFunctionAnalysisManager
&AM);
+
+ MachineFunctionProperties getRequiredProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
} // namespace llvm
#endif // #ifndef LLVM_CODEGEN_REGALLOCGREEDY_H_
diff --git a/llvm/lib/CodeGen/SplitKit.h b/llvm/include/llvm/CodeGen/SplitKit.h
similarity index 97%
rename from llvm/lib/CodeGen/SplitKit.h
rename to llvm/include/llvm/CodeGen/SplitKit.h
index cc277ecc0e882b..50b63b9aa2a858 100644
--- a/llvm/lib/CodeGen/SplitKit.h
+++ b/llvm/include/llvm/CodeGen/SplitKit.h
@@ -88,7 +88,6 @@ class LLVM_LIBRARY_VISIBILITY InsertPointAnalysis {
}
return Res;
}
-
};
/// SplitAnalysis - Analyze a LiveInterval, looking for live range splitting
@@ -387,7 +386,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// removeBackCopies - Remove the copy instructions that defines the values
/// in the vector in the complement interval.
- void removeBackCopies(SmallVectorImpl<VNInfo*> &Copies);
+ void removeBackCopies(SmallVectorImpl<VNInfo *> &Copies);
/// getShallowDominator - Returns the least busy dominator of MBB that is
/// also dominated by DefMBB. Busy is measured by loop depth.
@@ -430,8 +429,9 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// \p InsertBefore. This can be invoked with a \p LaneMask which may make it
/// necessary to construct a sequence of copies to cover it exactly.
SlotIndex buildCopy(Register FromReg, Register ToReg, LaneBitmask LaneMask,
- MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
- bool Late, unsigned RegIdx);
+ MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator InsertBefore, bool Late,
+ unsigned RegIdx);
SlotIndex buildSingleSubRegCopy(Register FromReg, Register ToReg,
MachineBasicBlock &MB,
@@ -448,7 +448,7 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
VirtRegAuxInfo &VRAI);
/// reset - Prepare for a new split.
- void reset(LiveRangeEdit&, ComplementSpillMode = SM_Partition);
+ void reset(LiveRangeEdit &, ComplementSpillMode = SM_Partition);
/// Create a new virtual register and live interval.
/// Return the interval index, starting from 1. Interval index 0 is the
@@ -533,9 +533,9 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// @param LeaveBefore When set, leave IntvIn before this point.
/// @param IntvOut Interval index leaving the block.
/// @param EnterAfter When set, enter IntvOut after this point.
- void splitLiveThroughBlock(unsigned MBBNum,
- unsigned IntvIn, SlotIndex LeaveBefore,
- unsigned IntvOut, SlotIndex EnterAfter);
+ void splitLiveThroughBlock(unsigned MBBNum, unsigned IntvIn,
+ SlotIndex LeaveBefore, unsigned IntvOut,
+ SlotIndex EnterAfter);
/// splitRegInBlock - Split CurLI in the given block such that it enters the
/// block in IntvIn and leaves it on the stack (or not at all). Split points
@@ -545,8 +545,8 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// @param BI Block descriptor.
/// @param IntvIn Interval index entering the block. Not 0.
/// @param LeaveBefore When set, leave IntvIn before this point.
- void splitRegInBlock(const SplitAnalysis::BlockInfo &BI,
- unsigned IntvIn, SlotIndex LeaveBefore);
+ void splitRegInBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvIn,
+ SlotIndex LeaveBefore);
/// splitRegOutBlock - Split CurLI in the given block such that it enters the
/// block on the stack (or isn't live-in at all) and leaves it in IntvOut.
@@ -557,8 +557,8 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
/// @param BI Block descriptor.
/// @param IntvOut Interval index leaving the block.
/// @param EnterAfter When set, enter IntvOut after this point.
- void splitRegOutBlock(const SplitAnalysis::BlockInfo &BI,
- unsigned IntvOut, SlotIndex EnterAfter);
+ void splitRegOutBlock(const SplitAnalysis::BlockInfo &BI, unsigned IntvOut,
+ SlotIndex EnterAfter);
};
} // end namespace llvm
diff --git a/llvm/include/llvm/InitializePasses.h
b/llvm/include/llvm/InitializePasses.h
index 87faf111a30cc9..1ab0ae27d54663 100644
--- a/llvm/include/llvm/InitializePasses.h
+++ b/llvm/include/llvm/InitializePasses.h
@@ -249,7 +249,7 @@ void
initializeProfileSummaryInfoWrapperPassPass(PassRegistry &);
void initializePromoteLegacyPassPass(PassRegistry &);
void initializeRABasicPass(PassRegistry &);
void initializePseudoProbeInserterPass(PassRegistry &);
-void initializeRAGreedyPass(PassRegistry &);
+void initializeRAGreedyLegacyPass(PassRegistry &);
void initializeReachingDefAnalysisPass(PassRegistry &);
void initializeReassociateLegacyPassPass(PassRegistry &);
void initializeRegAllocEvictionAdvisorAnalysisLegacyPass(PassRegistry &);
diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def
b/llvm/include/llvm/Passes/MachinePassRegistry.def
index c23e4af1a342bd..bf12a2c9aca90b 100644
--- a/llvm/include/llvm/Passes/MachinePassRegistry.def
+++ b/llvm/include/llvm/Passes/MachinePassRegistry.def
@@ -187,6 +187,15 @@ MACHINE_FUNCTION_PASS_WITH_PARAMS(
return parseRegAllocFastPassOptions(*PB, Params);
},
"filter=reg-filter;no-clear-vregs")
+
+MACHINE_FUNCTION_PASS_WITH_PARAMS(
+ "regallocgreedy", "RAGreedy",
+ [](RegAllocFilterFunc F) { return RAGreedyPass(F); },
+ [PB = this](StringRef Params) {
+ // TODO: parseRegAllocFilter(*PB, Params);
+ return Expected<RegAllocFilterFunc>(nullptr);
+ }, ""
+)
#undef MACHINE_FUNCTION_PASS_WITH_PARAMS
// After a pass is converted to new pass manager, its entry should be moved
from
diff --git a/llvm/lib/CodeGen/CodeGen.cpp b/llvm/lib/CodeGen/CodeGen.cpp
index 8efe540770913a..6acff9cd21134b 100644
--- a/llvm/lib/CodeGen/CodeGen.cpp
+++ b/llvm/lib/CodeGen/CodeGen.cpp
@@ -111,7 +111,7 @@ void llvm::initializeCodeGen(PassRegistry &Registry) {
initializePreISelIntrinsicLoweringLegacyPassPass(Registry);
initializeProcessImplicitDefsPass(Registry);
initializeRABasicPass(Registry);
- initializeRAGreedyPass(Registry);
+ initializeRAGreedyLegacyPass(Registry);
initializeRegAllocFastPass(Registry);
initializeRegUsageInfoCollectorLegacyPass(Registry);
initializeRegUsageInfoPropagationLegacyPass(Registry);
diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp
b/llvm/lib/CodeGen/InlineSpiller.cpp
index b9768d5c63a5d1..fedf15f86b6ba2 100644
--- a/llvm/lib/CodeGen/InlineSpiller.cpp
+++ b/llvm/lib/CodeGen/InlineSpiller.cpp
@@ -11,7 +11,6 @@
//
//===----------------------------------------------------------------------===//
-#include "SplitKit.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/ADT/MapVector.h"
@@ -36,6 +35,7 @@
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/Spiller.h"
+#include "llvm/CodeGen/SplitKit.h"
#include "llvm/CodeGen/StackMaps.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h"
diff --git a/llvm/lib/CodeGen/InterferenceCache.cpp
b/llvm/lib/CodeGen/InterferenceCache.cpp
index 73cde07cfd51a9..1455bb05e468c0 100644
--- a/llvm/lib/CodeGen/InterferenceCache.cpp
+++ b/llvm/lib/CodeGen/InterferenceCache.cpp
@@ -10,7 +10,7 @@
//
//===----------------------------------------------------------------------===//
-#include "InterferenceCache.h"
+#include "llvm/CodeGen/InterferenceCache.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
diff --git a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
index 5989d980eb4f44..f71a5ffb96f5f8 100644
--- a/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocEvictAdvisor.cpp
@@ -11,11 +11,11 @@
//===----------------------------------------------------------------------===//
#include "AllocationOrder.h"
-#include "RegAllocGreedy.h"
#include "llvm/Analysis/InteractiveModelRunner.h"
#include "llvm/Analysis/MLModelRunner.h"
#include "llvm/Analysis/TensorSpec.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#if defined(LLVM_HAVE_TF_AOT_REGALLOCEVICTMODEL) || defined(LLVM_HAVE_TFLITE)
#include "llvm/Analysis/ModelUnderTrainingRunner.h"
#include "llvm/Analysis/NoInferenceModelRunner.h"
diff --git a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
index dd598767f1bbc2..1bbd0ec2a73be0 100644
--- a/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
+++ b/llvm/lib/CodeGen/MLRegAllocPriorityAdvisor.cpp
@@ -11,7 +11,6 @@
//===----------------------------------------------------------------------===//
#include "AllocationOrder.h"
-#include "RegAllocGreedy.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/InteractiveModelRunner.h"
#include "llvm/Analysis/MLModelRunner.h"
@@ -24,6 +23,7 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp
b/llvm/lib/CodeGen/RegAllocBase.cpp
index 449033d6321003..6a98b27026f786 100644
--- a/llvm/lib/CodeGen/RegAllocBase.cpp
+++ b/llvm/lib/CodeGen/RegAllocBase.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "RegAllocBase.h"
+#include "llvm/CodeGen/RegAllocBase.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveInterval.h"
diff --git a/llvm/lib/CodeGen/RegAllocBasic.cpp
b/llvm/lib/CodeGen/RegAllocBasic.cpp
index f3f34f890be11e..66fd7693f7615d 100644
--- a/llvm/lib/CodeGen/RegAllocBasic.cpp
+++ b/llvm/lib/CodeGen/RegAllocBasic.cpp
@@ -12,7 +12,6 @@
//===----------------------------------------------------------------------===//
#include "AllocationOrder.h"
-#include "RegAllocBase.h"
#include "llvm/Analysis/AliasAnalysis.h"
#include "llvm/Analysis/ProfileSummaryInfo.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
@@ -26,6 +25,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/Passes.h"
+#include "llvm/CodeGen/RegAllocBase.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
#include "llvm/CodeGen/Spiller.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
diff --git a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
b/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
index 7e93bebed73bb7..f6f09a0e3c07e1 100644
--- a/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
+++ b/llvm/lib/CodeGen/RegAllocEvictionAdvisor.cpp
@@ -11,11 +11,11 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "AllocationOrder.h"
-#include "RegAllocGreedy.h"
#include "llvm/CodeGen/LiveRegMatrix.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
diff --git a/llvm/lib/CodeGen/RegAllocGreedy.cpp
b/llvm/lib/CodeGen/RegAllocGreedy.cpp
index 382521a895edcd..fb42ccbfba7977 100644
--- a/llvm/lib/CodeGen/RegAllocGreedy.cpp
+++ b/llvm/lib/CodeGen/RegAllocGreedy.cpp
@@ -11,11 +11,8 @@
//
//===----------------------------------------------------------------------===//
-#include "RegAllocGreedy.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#include "AllocationOrder.h"
-#include "InterferenceCache.h"
-#include "RegAllocBase.h"
-#include "SplitKit.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
@@ -26,6 +23,7 @@
#include "llvm/Analysis/OptimizationRemarkEmitter.h"
#include "llvm/CodeGen/CalcSpillWeights.h"
#include "llvm/CodeGen/EdgeBundles.h"
+#include "llvm/CodeGen/InterferenceCache.h"
#include "llvm/CodeGen/LiveDebugVariables.h"
#include "llvm/CodeGen/LiveInterval.h"
#include "llvm/CodeGen/LiveIntervalUnion.h"
@@ -43,7 +41,10 @@
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineOperand.h"
#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/RegAllocBase.h"
+#include "llvm/CodeGen/RegAllocCommon.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegAllocRegistry.h"
@@ -51,10 +52,12 @@
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/CodeGen/SpillPlacement.h"
#include "llvm/CodeGen/Spiller.h"
+#include "llvm/CodeGen/SplitKit.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/IR/DebugInfoMetadata.h"
#include "llvm/IR/Function.h"
#include "llvm/IR/LLVMContext.h"
@@ -146,11 +149,134 @@ static cl::opt<unsigned> SplitThresholdForRegWithHint(
static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
createGreedyRegisterAllocator);
-char RAGreedy::ID = 0;
-char &llvm::RAGreedyID = RAGreedy::ID;
+namespace {
+class RAGreedyLegacy : public MachineFunctionPass {
+ RegAllocFilterFunc F;
-INITIALIZE_PASS_BEGIN(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+public:
+ RAGreedyLegacy(const RegAllocFilterFunc F = nullptr);
+
+ static char ID;
+ /// Return the pass name.
+ StringRef getPassName() const override { return "Greedy Register Allocator";
}
+
+ /// RAGreedy analysis usage.
+ void getAnalysisUsage(AnalysisUsage &AU) const override;
+ /// Perform register allocation.
+ bool runOnMachineFunction(MachineFunction &mf) override;
+
+ MachineFunctionProperties getRequiredProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::NoPHIs);
+ }
+
+ MachineFunctionProperties getClearedProperties() const override {
+ return MachineFunctionProperties().set(
+ MachineFunctionProperties::Property::IsSSA);
+ }
+};
+
+} // end anonymous namespace
+
+RAGreedyLegacy::RAGreedyLegacy(const RegAllocFilterFunc F)
+ : MachineFunctionPass(ID), F(F) {
+ initializeRAGreedyLegacyPass(*PassRegistry::getPassRegistry());
+}
+
+RAGreedy::RAGreedy(const RegAllocFilterFunc F) : RegAllocBase(F) {}
+
+void RAGreedy::setAnalyses(RequiredAnalyses &Analyses) {
+ VRM = Analyses.VRM;
+ LIS = Analyses.LIS;
+ Matrix = Analyses.LRM;
+ Indexes = Analyses.Indexes;
+ MBFI = Analyses.MBFI;
+ DomTree = Analyses.DomTree;
+ Loops = Analyses.Loops;
+ ORE = Analyses.ORE;
+ Bundles = Analyses.Bundles;
+ SpillPlacer = Analyses.SpillPlacer;
+ DebugVars = Analyses.DebugVars;
+ LSS = Analyses.LSS;
+ EvictProvider = Analyses.EvictProvider;
+ PriorityProvider = Analyses.PriorityProvider;
+}
+
+PreservedAnalyses RAGreedyPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ MFPropsModifier _(*this, MF);
+
+ RAGreedy Impl(Filter);
+ RAGreedy::RequiredAnalyses Analyses;
+
+ Analyses.VRM = &MFAM.getResult<VirtRegMapAnalysis>(MF);
+ Analyses.LIS = &MFAM.getResult<LiveIntervalsAnalysis>(MF);
+ Analyses.LRM = &MFAM.getResult<LiveRegMatrixAnalysis>(MF);
+ Analyses.LSS = &MFAM.getResult<LiveStacksAnalysis>(MF);
+ Analyses.Indexes = &MFAM.getResult<SlotIndexesAnalysis>(MF);
+ Analyses.MBFI = &MFAM.getResult<MachineBlockFrequencyAnalysis>(MF);
+ Analyses.DomTree = &MFAM.getResult<MachineDominatorTreeAnalysis>(MF);
+ Analyses.ORE = &MFAM.getResult<MachineOptimizationRemarkEmitterAnalysis>(MF);
+ Analyses.Loops = &MFAM.getResult<MachineLoopAnalysis>(MF);
+ Analyses.Bundles = &MFAM.getResult<EdgeBundlesAnalysis>(MF);
+ Analyses.SpillPlacer = &MFAM.getResult<SpillPlacementAnalysis>(MF);
+ Analyses.DebugVars = &MFAM.getResult<LiveDebugVariablesAnalysis>(MF);
+ Analyses.EvictProvider =
+ MFAM.getResult<RegAllocEvictionAdvisorAnalysis>(MF).Provider;
+ Analyses.PriorityProvider =
+ MFAM.getResult<RegAllocPriorityAdvisorAnalysis>(MF).Provider;
+
+ Impl.setAnalyses(Analyses);
+ bool Changed = Impl.run(MF);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ auto PA = getMachineFunctionPassPreservedAnalyses();
+ PA.preserveSet<CFGAnalyses>();
+ PA.preserve<MachineBlockFrequencyAnalysis>();
+ PA.preserve<LiveIntervalsAnalysis>();
+ PA.preserve<SlotIndexesAnalysis>();
+ PA.preserve<LiveDebugVariablesAnalysis>();
+ PA.preserve<LiveStacksAnalysis>();
+ PA.preserve<MachineDominatorTreeAnalysis>();
+ PA.preserve<MachineLoopAnalysis>();
+ PA.preserve<VirtRegMapAnalysis>();
+ PA.preserve<LiveRegMatrixAnalysis>();
+ return PA;
+}
+
+bool RAGreedyLegacy::runOnMachineFunction(MachineFunction &MF) {
+ RAGreedy Impl(F);
+
+ RAGreedy::RequiredAnalyses Analyses;
+ Analyses.VRM = &getAnalysis<VirtRegMapWrapperLegacy>().getVRM();
+ Analyses.LIS = &getAnalysis<LiveIntervalsWrapperPass>().getLIS();
+ Analyses.LSS = &getAnalysis<LiveStacksWrapperLegacy>().getLS();
+ Analyses.LRM = &getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM();
+ Analyses.Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
+ Analyses.MBFI =
+ &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
+ Analyses.DomTree =
+ &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ Analyses.ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
+ Analyses.Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
+ Analyses.Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
+ Analyses.SpillPlacer =
+ &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
+ Analyses.DebugVars =
&getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
+ Analyses.EvictProvider =
+ getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider().get();
+ Analyses.PriorityProvider =
+ getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>().getProvider().get();
+
+ Impl.setAnalyses(Analyses);
+ return Impl.run(MF);
+}
+
+char RAGreedyLegacy::ID = 0;
+char &llvm::RAGreedyLegacyID = RAGreedyLegacy::ID;
+
+INITIALIZE_PASS_BEGIN(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
INITIALIZE_PASS_DEPENDENCY(LiveDebugVariablesWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(SlotIndexesWrapperPass)
INITIALIZE_PASS_DEPENDENCY(LiveIntervalsWrapperPass)
@@ -166,8 +292,8 @@ INITIALIZE_PASS_DEPENDENCY(SpillPlacementWrapperLegacy)
INITIALIZE_PASS_DEPENDENCY(MachineOptimizationRemarkEmitterPass)
INITIALIZE_PASS_DEPENDENCY(RegAllocEvictionAdvisorAnalysisLegacy)
INITIALIZE_PASS_DEPENDENCY(RegAllocPriorityAdvisorAnalysisLegacy)
-INITIALIZE_PASS_END(RAGreedy, "greedy",
- "Greedy Register Allocator", false, false)
+INITIALIZE_PASS_END(RAGreedyLegacy, "greedy", "Greedy Register Allocator",
+ false, false)
#ifndef NDEBUG
const char *const RAGreedy::StageName[] = {
@@ -186,17 +312,14 @@ const char *const RAGreedy::StageName[] = {
const float Hysteresis = (2007 / 2048.0f); // 0.97998046875
FunctionPass* llvm::createGreedyRegisterAllocator() {
- return new RAGreedy();
+ return new RAGreedyLegacy();
}
FunctionPass *llvm::createGreedyRegisterAllocator(RegAllocFilterFunc Ftor) {
- return new RAGreedy(Ftor);
+ return new RAGreedyLegacy(Ftor);
}
-RAGreedy::RAGreedy(RegAllocFilterFunc F)
- : MachineFunctionPass(ID), RegAllocBase(F) {}
-
-void RAGreedy::getAnalysisUsage(AnalysisUsage &AU) const {
+void RAGreedyLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
AU.addRequired<MachineBlockFrequencyInfoWrapperPass>();
AU.addPreserved<MachineBlockFrequencyInfoWrapperPass>();
@@ -1051,7 +1174,8 @@ void RAGreedy::splitAroundRegion(LiveRangeEdit &LREdit,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around region", &errs());
+ MF->verify(LIS, Indexes, "After splitting live range around region",
+ &errs());
}
MCRegister RAGreedy::tryRegionSplit(const LiveInterval &VirtReg,
@@ -1320,7 +1444,8 @@ unsigned RAGreedy::tryBlockSplit(const LiveInterval
&VirtReg,
}
if (VerifyEnabled)
- MF->verify(this, "After splitting live range around basic blocks",
&errs());
+ MF->verify(LIS, Indexes, "After splitting live range around basic blocks",
+ &errs());
return 0;
}
@@ -2507,7 +2632,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval
&VirtReg,
DebugVars->splitRegister(r, LRE.regs(), *LIS);
if (VerifyEnabled)
- MF->verify(this, "After spilling", &errs());
+ MF->verify(LIS, Indexes, "After spilling", &errs());
}
// The live virtual register requesting allocation was spilled, so tell
@@ -2703,7 +2828,7 @@ bool RAGreedy::hasVirtRegAlloc() {
return false;
}
-bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
+bool RAGreedy::run(MachineFunction &mf) {
LLVM_DEBUG(dbgs() << "********** GREEDY REGISTER ALLOCATION **********\n"
<< "********** Function: " << mf.getName() << '\n');
@@ -2711,29 +2836,18 @@ bool RAGreedy::runOnMachineFunction(MachineFunction
&mf) {
TII = MF->getSubtarget().getInstrInfo();
if (VerifyEnabled)
- MF->verify(this, "Before greedy register allocator", &errs());
+ MF->verify(LIS, Indexes, "Before greedy register allocator", &errs());
- RegAllocBase::init(getAnalysis<VirtRegMapWrapperLegacy>().getVRM(),
- getAnalysis<LiveIntervalsWrapperPass>().getLIS(),
- getAnalysis<LiveRegMatrixWrapperLegacy>().getLRM());
+ RegAllocBase::init(*this->VRM, *this->LIS, *this->Matrix);
// Early return if there is no virtual register to be allocated to a
// physical register.
if (!hasVirtRegAlloc())
return false;
- Indexes = &getAnalysis<SlotIndexesWrapperPass>().getSI();
// Renumber to get accurate and consistent results from
// SlotIndexes::getApproxInstrDistance.
Indexes->packIndexes();
- MBFI = &getAnalysis<MachineBlockFrequencyInfoWrapperPass>().getMBFI();
- DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
- ORE = &getAnalysis<MachineOptimizationRemarkEmitterPass>().getORE();
- Loops = &getAnalysis<MachineLoopInfoWrapperPass>().getLI();
- Bundles = &getAnalysis<EdgeBundlesWrapperLegacy>().getEdgeBundles();
- SpillPlacer = &getAnalysis<SpillPlacementWrapperLegacy>().getResult();
- DebugVars = &getAnalysis<LiveDebugVariablesWrapperLegacy>().getLDV();
- auto &LSS = getAnalysis<LiveStacksWrapperLegacy>().getLS();
initializeCSRCost();
@@ -2748,15 +2862,13 @@ bool RAGreedy::runOnMachineFunction(MachineFunction
&mf) {
: TRI->reverseLocalAssignment();
ExtraInfo.emplace();
- EvictAdvisor =
-
getAnalysis<RegAllocEvictionAdvisorAnalysisLegacy>().getProvider()->getAdvisor(*MF,
*this);
- PriorityAdvisor = getAnalysis<RegAllocPriorityAdvisorAnalysisLegacy>()
- .getProvider()
- ->getAdvisor(*MF, *this);
+
+ EvictAdvisor = EvictProvider->getAdvisor(*MF, *this);
+ PriorityAdvisor = PriorityProvider->getAdvisor(*MF, *this);
VRAI = std::make_unique<VirtRegAuxInfo>(*MF, *LIS, *VRM, *Loops, *MBFI);
SpillerInstance.reset(
- createInlineSpiller({*LIS, LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
+ createInlineSpiller({*LIS, *LSS, *DomTree, *MBFI}, *MF, *VRM, *VRAI));
VRAI->calculateSpillWeightsAndHints();
@@ -2773,7 +2885,7 @@ bool RAGreedy::runOnMachineFunction(MachineFunction &mf) {
tryHintsRecoloring();
if (VerifyEnabled)
- MF->verify(this, "Before post optimization", &errs());
+ MF->verify(LIS, Indexes, "Before post optimization", &errs());
postOptimization();
reportStats();
diff --git a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
index 6699da052de5cf..b76d0b3a15b015 100644
--- a/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
+++ b/llvm/lib/CodeGen/RegAllocPriorityAdvisor.cpp
@@ -11,8 +11,8 @@
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
-#include "RegAllocGreedy.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#include "llvm/CodeGen/VirtRegMap.h"
#include "llvm/IR/Module.h"
#include "llvm/InitializePasses.h"
diff --git a/llvm/lib/CodeGen/SplitKit.cpp b/llvm/lib/CodeGen/SplitKit.cpp
index eb33b93c197d7c..5cdb1325662bdf 100644
--- a/llvm/lib/CodeGen/SplitKit.cpp
+++ b/llvm/lib/CodeGen/SplitKit.cpp
@@ -11,7 +11,7 @@
//
//===----------------------------------------------------------------------===//
-#include "SplitKit.h"
+#include "llvm/CodeGen/SplitKit.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LiveRangeEdit.h"
diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp
index e1aa1497891506..bcf1d9d677182c 100644
--- a/llvm/lib/Passes/PassBuilder.cpp
+++ b/llvm/lib/Passes/PassBuilder.cpp
@@ -125,6 +125,7 @@
#include "llvm/CodeGen/PreISelIntrinsicLowering.h"
#include "llvm/CodeGen/RegAllocEvictionAdvisor.h"
#include "llvm/CodeGen/RegAllocFast.h"
+#include "llvm/CodeGen/RegAllocGreedy.h"
#include "llvm/CodeGen/RegAllocPriorityAdvisor.h"
#include "llvm/CodeGen/RegUsageInfoCollector.h"
#include "llvm/CodeGen/RegUsageInfoPropagate.h"
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