Author: Thorsten Schütt Date: 2024-12-05T07:03:46+01:00 New Revision: d999ae6cfdae05ee22a7df13e8a70ce14fc96684
URL: https://github.com/llvm/llvm-project/commit/d999ae6cfdae05ee22a7df13e8a70ce14fc96684 DIFF: https://github.com/llvm/llvm-project/commit/d999ae6cfdae05ee22a7df13e8a70ce14fc96684.diff LOG: Revert "[GlobalISel] Combine [s,z]ext of undef into 0 (#117439)" This reverts commit 45162635bf657eb0a6cdebc6398fada974981c64. Added: Modified: llvm/include/llvm/Target/GlobalISel/Combine.td llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir llvm/test/CodeGen/AArch64/extract-vector-elt.ll llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll Removed: ################################################################################ diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index dbdc007d9c6fec8..b0c63fc7c7b806d 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -428,7 +428,7 @@ def unary_undef_to_zero: GICombineRule< // replaced with undef. def propagate_undef_any_op: GICombineRule< (defs root:$root), - (match (wip_match_opcode G_ADD, G_FPTOSI, G_FPTOUI, G_SUB, G_XOR, G_TRUNC, G_BITCAST):$root, + (match (wip_match_opcode G_ADD, G_FPTOSI, G_FPTOUI, G_SUB, G_XOR, G_TRUNC, G_BITCAST, G_ANYEXT):$root, [{ return Helper.matchAnyExplicitUseIsUndef(*${root}); }]), (apply [{ Helper.replaceInstWithUndef(*${root}); }])>; @@ -1857,26 +1857,6 @@ class integer_of_opcode<Instruction castOpcode> : GICombineRule < def integer_of_truncate : integer_of_opcode<G_TRUNC>; -def anyext_undef: GICombineRule< - (defs root:$root), - (match (G_IMPLICIT_DEF $undef), - (G_ANYEXT $root, $undef):$Aext), - (apply [{ Helper.replaceInstWithUndef(*${Aext}); }])>; - -def zext_undef: GICombineRule< - (defs root:$root), - (match (G_IMPLICIT_DEF $undef), - (G_ZEXT $root, $undef):$Zext, - [{ return Helper.isConstantLegalOrBeforeLegalizer(MRI.getType(${Zext}->getOperand(0).getReg())); }]), - (apply [{ Helper.replaceInstWithConstant(*${Zext}, 0); }])>; - -def sext_undef: GICombineRule< - (defs root:$root), - (match (G_IMPLICIT_DEF $undef), - (G_SEXT $root, $undef):$Sext, - [{ return Helper.isConstantLegalOrBeforeLegalizer(MRI.getType(${Sext}->getOperand(0).getReg())); }]), - (apply [{ Helper.replaceInstWithConstant(*${Sext}, 0); }])>; - def cast_of_cast_combines: GICombineGroup<[ truncate_of_zext, truncate_of_sext, @@ -1902,10 +1882,7 @@ def cast_combines: GICombineGroup<[ narrow_binop_and, narrow_binop_or, narrow_binop_xor, - integer_of_truncate, - anyext_undef, - sext_undef, - zext_undef + integer_of_truncate ]>; def canonicalize_icmp : GICombineRule< diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir index 25161652dafac4e..b045deebc56e03c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-cast.mir @@ -217,55 +217,3 @@ body: | %large:_(<2 x s64>) = G_ANYEXT %bv(<2 x s32>) $q0 = COPY %large(<2 x s64>) $d0 = COPY %bv(<2 x s32>) -... ---- -name: test_combine_anyext_undef -legalized: true -body: | - bb.1: - ; CHECK-PRE-LABEL: name: test_combine_anyext_undef - ; CHECK-PRE: %aext:_(s64) = G_IMPLICIT_DEF - ; CHECK-PRE-NEXT: $x0 = COPY %aext(s64) - ; - ; CHECK-POST-LABEL: name: test_combine_anyext_undef - ; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF - ; CHECK-POST-NEXT: %aext:_(s64) = G_ANYEXT %undef(s32) - ; CHECK-POST-NEXT: $x0 = COPY %aext(s64) - %undef:_(s32) = G_IMPLICIT_DEF - %aext:_(s64) = G_ANYEXT %undef(s32) - $x0 = COPY %aext(s64) -... ---- -name: test_combine_sext_undef -legalized: true -body: | - bb.1: - ; CHECK-PRE-LABEL: name: test_combine_sext_undef - ; CHECK-PRE: %sext:_(s64) = G_CONSTANT i64 0 - ; CHECK-PRE-NEXT: $x0 = COPY %sext(s64) - ; - ; CHECK-POST-LABEL: name: test_combine_sext_undef - ; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF - ; CHECK-POST-NEXT: %sext:_(s64) = G_SEXT %undef(s32) - ; CHECK-POST-NEXT: $x0 = COPY %sext(s64) - %undef:_(s32) = G_IMPLICIT_DEF - %sext:_(s64) = G_SEXT %undef(s32) - $x0 = COPY %sext(s64) -... ---- -name: test_combine_zext_undef -legalized: true -body: | - bb.1: - ; CHECK-PRE-LABEL: name: test_combine_zext_undef - ; CHECK-PRE: %zext:_(s64) = G_CONSTANT i64 0 - ; CHECK-PRE-NEXT: $x0 = COPY %zext(s64) - ; - ; CHECK-POST-LABEL: name: test_combine_zext_undef - ; CHECK-POST: %undef:_(s32) = G_IMPLICIT_DEF - ; CHECK-POST-NEXT: %zext:_(s64) = G_ZEXT %undef(s32) - ; CHECK-POST-NEXT: $x0 = COPY %zext(s64) - %undef:_(s32) = G_IMPLICIT_DEF - %zext:_(s64) = G_ZEXT %undef(s32) - $x0 = COPY %zext(s64) -... diff --git a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll index e89e1516fb1f541..5e5fdd6d317057e 100644 --- a/llvm/test/CodeGen/AArch64/extract-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/extract-vector-elt.ll @@ -8,10 +8,17 @@ ; CHECK-GI-NEXT: warning: Instruction selection used fallback path for extract_v4i32_vector_extract_const define i64 @extract_v2i64_undef_index(<2 x i64> %a, i32 %c) { -; CHECK-LABEL: extract_v2i64_undef_index: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: extract_v2i64_undef_index: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: extract_v2i64_undef_index: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: str q0, [sp, #-16]! +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: ldr x0, [sp], #16 +; CHECK-GI-NEXT: ret entry: %d = extractelement <2 x i64> %a, i32 undef ret i64 %d diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir index 9b39afd32ac3789..7893bfa1d38f08f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-amdgpu-cvt-f32-ubyte.mir @@ -261,7 +261,8 @@ body: | ; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_16 ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16) ; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext ; CHECK-NEXT: $vgpr0 = COPY %result(s32) %arg:_(s32) = COPY $vgpr0 @@ -283,7 +284,8 @@ body: | ; CHECK-LABEL: name: cvt_f32_ubyte0_zext_lshr_24 ; CHECK: liveins: $vgpr0 ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: %zext:_(s32) = G_CONSTANT i32 0 + ; CHECK-NEXT: %shift:_(s16) = G_IMPLICIT_DEF + ; CHECK-NEXT: %zext:_(s32) = G_ZEXT %shift(s16) ; CHECK-NEXT: %result:_(s32) = G_AMDGPU_CVT_F32_UBYTE0 %zext ; CHECK-NEXT: $vgpr0 = COPY %result(s32) %arg:_(s32) = COPY $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll index 384a2c63122b859..a1a466fb04440d3 100644 --- a/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll +++ b/llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll @@ -4074,12 +4074,14 @@ define amdgpu_kernel void @v_test_v2i16_x_add_undef_neg32(ptr addrspace(1) %out, ; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-GISEL-NEXT: flat_load_dword v3, v[0:1] ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 -; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; VI-GISEL-NEXT: v_not_b32_e32 v2, 31 +; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; VI-GISEL-NEXT: s_and_b32 s0, 0xffff, s0 ; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) ; VI-GISEL-NEXT: v_add_u16_sdwa v2, v3, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD +; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2 ; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 ; VI-GISEL-NEXT: s_endpgm ; @@ -4189,12 +4191,15 @@ define amdgpu_kernel void @v_test_v2i16_x_add_neg32_undef(ptr addrspace(1) %out, ; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-GISEL-NEXT: flat_load_dword v3, v[0:1] +; VI-GISEL-NEXT: s_and_b32 s2, 0xffff, s0 ; VI-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; VI-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; VI-GISEL-NEXT: v_add_u32_e32 v0, vcc, v0, v2 +; VI-GISEL-NEXT: s_lshl_b32 s0, s2, 16 ; VI-GISEL-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-GISEL-NEXT: s_waitcnt vmcnt(0) ; VI-GISEL-NEXT: v_add_u16_e32 v2, 0xffe0, v3 +; VI-GISEL-NEXT: v_or_b32_e32 v2, s0, v2 ; VI-GISEL-NEXT: flat_store_dword v[0:1], v2 ; VI-GISEL-NEXT: s_endpgm ; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
