llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: None (llvmbot) <details> <summary>Changes</summary> Backport 71b6f6b8a1cd9a63b9d382fe15f40bbb427939b9 408c84f35b8b0338b630a6ee313c14238e62b5e6 Requested by: @<!-- -->topperc --- Full diff: https://github.com/llvm/llvm-project/pull/117948.diff 5 Files Affected: - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.cpp (+7) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+8-9) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td (+3-2) - (modified) llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll (+1-3) - (modified) llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll (+1-3) ``````````diff diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 6c0cbeadebf431..7f4bbe7861087e 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -2536,6 +2536,13 @@ bool RISCVInstrInfo::verifyInstruction(const MachineInstr &MI, } } + if (int Idx = RISCVII::getFRMOpNum(Desc); + Idx >= 0 && MI.getOperand(Idx).getImm() == RISCVFPRndMode::DYN && + !MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { + ErrInfo = "dynamic rounding mode should read FRM"; + return false; + } + return true; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index b860273d639ee5..93fd0b2aada35a 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -6471,7 +6471,7 @@ defm PseudoVFRDIV : VPseudoVFRDIV_VF_RM; //===----------------------------------------------------------------------===// // 13.5. Vector Widening Floating-Point Multiply //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in { +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM; } @@ -6504,7 +6504,7 @@ defm PseudoVFWMACCBF16 : VPseudoVWMAC_VV_VF_BF_RM; //===----------------------------------------------------------------------===// // 13.8. Vector Floating-Point Square-Root Instruction //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in defm PseudoVFSQRT : VPseudoVSQR_V_RM; //===----------------------------------------------------------------------===// @@ -6516,7 +6516,7 @@ defm PseudoVFRSQRT7 : VPseudoVRCP_V; //===----------------------------------------------------------------------===// // 13.10. Vector Floating-Point Reciprocal Estimate Instruction //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, hasSideEffects = 0 in +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in defm PseudoVFREC7 : VPseudoVRCP_V_RM; //===----------------------------------------------------------------------===// @@ -6627,9 +6627,10 @@ defm PseudoVFNCVT_F_X : VPseudoVNCVTF_W_RM; defm PseudoVFNCVT_RM_F_XU : VPseudoVNCVTF_RM_W; defm PseudoVFNCVT_RM_F_X : VPseudoVNCVTF_RM_W; -let hasSideEffects = 0, hasPostISelHook = 1 in +let hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFNCVT_F_F : VPseudoVNCVTD_W_RM; defm PseudoVFNCVTBF16_F_F : VPseudoVNCVTD_W_RM; +} defm PseudoVFNCVT_ROD_F_F : VPseudoVNCVTD_W; } // mayRaiseFPException = true @@ -6665,8 +6666,7 @@ let Predicates = [HasVInstructionsAnyF] in { //===----------------------------------------------------------------------===// // 14.3. Vector Single-Width Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let mayRaiseFPException = true, - hasSideEffects = 0 in { +let mayRaiseFPException = true, hasSideEffects = 0, hasPostISelHook = 1 in { defm PseudoVFREDOSUM : VPseudoVFREDO_VS_RM; defm PseudoVFREDUSUM : VPseudoVFRED_VS_RM; } @@ -6678,9 +6678,8 @@ defm PseudoVFREDMAX : VPseudoVFREDMINMAX_VS; //===----------------------------------------------------------------------===// // 14.4. Vector Widening Floating-Point Reduction Instructions //===----------------------------------------------------------------------===// -let IsRVVWideningReduction = 1, - hasSideEffects = 0, - mayRaiseFPException = true in { +let IsRVVWideningReduction = 1, hasSideEffects = 0, mayRaiseFPException = true, + hasPostISelHook = 1 in { defm PseudoVFWREDUSUM : VPseudoVFWRED_VS_RM; defm PseudoVFWREDOSUM : VPseudoVFWREDO_VS_RM; } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td index 71aa1f19e089a9..eacc75b9a6c445 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td @@ -217,7 +217,8 @@ let Predicates = [HasVendorXSfvfwmaccqqq], DecoderNamespace = "XSfvfwmaccqqq" in def VFWMACC_4x4x4 : CustomSiFiveVMACC<0b111100, OPFVV, "sf.vfwmacc.4x4x4">; } -let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf" in { +let Predicates = [HasVendorXSfvfnrclipxfqf], DecoderNamespace = "XSfvfnrclipxfqf", + Uses = [FRM] in { def VFNRCLIP_XU_F_QF : CustomSiFiveVFNRCLIP<0b100010, OPFVF, "sf.vfnrclip.xu.f.qf">; def VFNRCLIP_X_F_QF : CustomSiFiveVFNRCLIP<0b100011, OPFVF, "sf.vfnrclip.x.f.qf">; } @@ -399,7 +400,7 @@ multiclass VPseudoSiFiveVFWMACC<string Constraint = ""> { multiclass VPseudoSiFiveVFNRCLIP<string Constraint = "@earlyclobber $rd"> { foreach i = 0-4 in - let hasSideEffects = 0 in + let hasSideEffects = 0, hasPostISelHook = 1 in defm "Pseudo" # NAME : VPseudoBinaryRoundingMode<MxListW[i].vrclass, MxListVF4[i].vrclass, FPR32, MxListW[i], diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll index 3c19616576f55d..fbe1a97c201cf3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll @@ -13,10 +13,8 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen( define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -24,7 +22,7 @@ entry: <vscale x 1 x i8> undef, <vscale x 1 x float> %0, float %1, - iXLen 0, iXLen %2) + iXLen 7, iXLen %2) ret <vscale x 1 x i8> %a } diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll index dbcee311c6e35f..dfb0ccd982e845 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll @@ -13,10 +13,8 @@ declare <vscale x 1 x i8> @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen( define <vscale x 1 x i8> @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32(<vscale x 1 x float> %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -24,7 +22,7 @@ entry: <vscale x 1 x i8> undef, <vscale x 1 x float> %0, float %1, - iXLen 0, iXLen %2) + iXLen 7, iXLen %2) ret <vscale x 1 x i8> %a } `````````` </details> https://github.com/llvm/llvm-project/pull/117948 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
