================
@@ -1397,6 +1397,19 @@ The AMDGPU backend implements the following LLVM IR
intrinsics.
used by hardware to control
active lanes when used in EXEC register.
For example, ballot(i1
true) return EXEC mask.
+ llvm.amdgcn.mfma.f32.16x16x128.f8f6f4.scaled Emit
`v_mfma_f32_16x16x128_f8f6f4`, bundled with a `v_mfma_ld_scale_b32`
----------------
shiltian wrote:
This reminds me that we probably didn't add other gfx950 intrinsics to the
document.
https://github.com/llvm/llvm-project/pull/116723
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