https://github.com/Akshat-Oke updated
https://github.com/llvm/llvm-project/pull/110229
>From 2b877142d7a9346033d02e5a977d2dcaa440258c Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Wed, 9 Oct 2024 05:01:22 +0000
Subject: [PATCH 1/7] [MIR] Add missing noteNewVirtualRegister callbacks
---
llvm/lib/CodeGen/MIRParser/MIParser.cpp | 1 +
llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 9 +++++----
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index f1d3ce9a563406..7aaa0f409d5ef9 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1786,6 +1786,7 @@ bool MIParser::parseRegisterOperand(MachineOperand &Dest,
MRI.setRegClassOrRegBank(Reg, static_cast<RegisterBank *>(nullptr));
MRI.setType(Reg, Ty);
+ MRI.noteNewVirtualRegister(Reg);
}
}
} else if (consumeIfPresent(MIToken::lparen)) {
diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
index 0c8a3eb6c2d83d..f10a480f7e6160 100644
--- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -652,10 +652,10 @@ MIRParserImpl::initializeMachineFunction(const
yaml::MachineFunction &YamlMF,
bool MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
const yaml::MachineFunction &YamlMF) {
MachineFunction &MF = PFS.MF;
- MachineRegisterInfo &RegInfo = MF.getRegInfo();
+ MachineRegisterInfo &MRI = MF.getRegInfo();
assert(RegInfo.tracksLiveness());
if (!YamlMF.TracksRegLiveness)
- RegInfo.invalidateLiveness();
+ MRI.invalidateLiveness();
SMDiagnostic Error;
// Parse the virtual register information.
@@ -705,6 +705,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
FlagStringValue.Value + "'");
Info.Flags.push_back(FlagValue);
}
+ MRI.noteNewVirtualRegister(Info.VReg);
}
// Parse the liveins.
@@ -720,7 +721,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, LiveIn.VirtualRegister.SourceRange);
VReg = Info->VReg;
}
- RegInfo.addLiveIn(Reg, VReg);
+ MRI.addLiveIn(Reg, VReg);
}
// Parse the callee saved registers (Registers that will
@@ -733,7 +734,7 @@ bool
MIRParserImpl::parseRegisterInfo(PerFunctionMIParsingState &PFS,
return error(Error, RegSource.SourceRange);
CalleeSavedRegisters.push_back(Reg);
}
- RegInfo.setCalleeSavedRegs(CalleeSavedRegisters);
+ MRI.setCalleeSavedRegs(CalleeSavedRegisters);
}
return false;
>From 553d5139960f0a26a5d3014fe36179c4ae0cf49d Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Fri, 27 Sep 2024 08:58:39 +0000
Subject: [PATCH 2/7] [AMDGPU] Serialize WWM_REG vreg flag
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 15 +++++++++++++++
llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++--
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 11 +++++++++++
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 10 ++++++++++
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16 ++++++++++++++++
5 files changed, 54 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index 2c84cdac76d027..b23fea33183354 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1716,6 +1716,21 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
MFI->reserveWWMRegister(ParsedReg);
}
+ auto setRegisterFlags = [&](const VRegInfo &Info) {
+ for (const auto &Flag : Info.Flags) {
+ MFI->setFlag(Info.VReg, Flag);
+ }
+ };
+
+ for (const auto &P : PFS.VRegInfosNamed) {
+ const VRegInfo &Info = *P.second;
+ setRegisterFlags(Info);
+ }
+ for (const auto &P : PFS.VRegInfos) {
+ const VRegInfo &Info = *P.second;
+ setRegisterFlags(Info);
+ }
+
auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
const TargetRegisterClass &RC,
ArgDescriptor &Arg, unsigned UserSGPRs,
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index c8c305e24c7101..ec09a2803ed09c 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -696,8 +696,8 @@ class SIMachineFunctionInfo final : public
AMDGPUMachineFunction,
void setFlag(Register Reg, uint8_t Flag) {
assert(Reg.isVirtual());
- if (VRegFlags.inBounds(Reg))
- VRegFlags[Reg] |= Flag;
+ VRegFlags.grow(Reg);
+ VRegFlags[Reg] |= Flag;
}
bool checkFlag(Register Reg, uint8_t Flag) const {
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index de9cbe403ab618..6b6750af1d86cb 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3851,3 +3851,14 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
}
return 0;
}
+
+SmallVector<std::string>
+SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
+ const MachineFunction &MF) const {
+ SmallVector<std::string> RegFlags;
+ const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
+ if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
+ RegFlags.push_back("WWM_REG");
+ }
+ return RegFlags;
+}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 99fa632c0300be..fe3bbe839e9373 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -457,6 +457,16 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
// No check if the subreg is supported by the current RC is made.
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
+
+ std::pair<bool, uint8_t> getVRegFlagValue(StringRef Name) const override {
+ if (Name == "WWM_REG") {
+ return {true, AMDGPU::VirtRegFlag::WWM_REG};
+ }
+ return {false, 0};
+ }
+
+ SmallVector<std::string>
+ getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
namespace AMDGPU {
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
new file mode 100644
index 00000000000000..3ea8f6eafcf10c
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
@@ -0,0 +1,16 @@
+# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
+# This test ensures that the MIR parser parses virtual register flags correctly
+
+---
+name: vregs
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
+# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+body: |
+ bb.0:
+ %2:sgpr_64 = COPY %1
+ %1:sgpr_64 = COPY %0
>From faea2a07529ca4f29f2c5d29d1450ce62f30353d Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Fri, 4 Oct 2024 06:31:06 +0000
Subject: [PATCH 3/7] Correct TRI methods to optional<> and SmallString
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 6 +++---
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 8 ++++----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 6b6750af1d86cb..ba29c574c2621e 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3852,13 +3852,13 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
return 0;
}
-SmallVector<std::string>
+SmallVector<SmallString<8>>
SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
const MachineFunction &MF) const {
- SmallVector<std::string> RegFlags;
+ SmallVector<SmallString<8>> RegFlags;
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
- RegFlags.push_back("WWM_REG");
+ RegFlags.push_back(SmallString<8>("WWM_REG"));
}
return RegFlags;
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index fe3bbe839e9373..f2e2828850713d 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -458,14 +458,14 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo
{
unsigned getSubRegAlignmentNumBits(const TargetRegisterClass *RC,
unsigned SubReg) const;
- std::pair<bool, uint8_t> getVRegFlagValue(StringRef Name) const override {
+ std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override {
if (Name == "WWM_REG") {
- return {true, AMDGPU::VirtRegFlag::WWM_REG};
+ return AMDGPU::VirtRegFlag::WWM_REG;
}
- return {false, 0};
+ return {};
}
- SmallVector<std::string>
+ SmallVector<SmallString<8>>
getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
>From 8611a3d511b31cf7cc95f7e89f631eb9810d33fc Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Fri, 4 Oct 2024 06:31:42 +0000
Subject: [PATCH 4/7] Move test to MIR/AMDGPU/mfi-no-ir
---
llvm/test/CodeGen/AMDGPU/virtual-registers.mir | 16 ----------------
.../MIR/AMDGPU/machine-function-info-no-ir.mir | 15 +++++++++++++++
2 files changed, 15 insertions(+), 16 deletions(-)
delete mode 100644 llvm/test/CodeGen/AMDGPU/virtual-registers.mir
diff --git a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
b/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
deleted file mode 100644
index 3ea8f6eafcf10c..00000000000000
--- a/llvm/test/CodeGen/AMDGPU/virtual-registers.mir
+++ /dev/null
@@ -1,16 +0,0 @@
-# RUN: llc -mtriple=amdgcn -run-pass=none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses virtual register flags correctly
-
----
-name: vregs
-# CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1',
flags: [ WWM_REG ] }
-# CHECK-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
-# CHECK-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ]
}
-registers:
- - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
- - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
-body: |
- bb.0:
- %2:sgpr_64 = COPY %1
- %1:sgpr_64 = COPY %0
diff --git a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
index ebbb89b7816c58..51795a4fea515e 100644
--- a/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
+++ b/llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-no-ir.mir
@@ -578,3 +578,18 @@ body: |
SI_RETURN
...
+---
+name: vregs
+# FULL: registers:
+# FULL-NEXT: - { id: 0, class: vgpr_32, preferred-register: '$vgpr1', flags:
[ WWM_REG ] }
+# FULL-NEXT: - { id: 1, class: sgpr_64, preferred-register: '$sgpr0_sgpr1',
flags: [ ] }
+# FULL-NEXT: - { id: 2, class: sgpr_64, preferred-register: '', flags: [ ] }
+registers:
+ - { id: 0, class: vgpr_32, preferred-register: $vgpr1, flags: [ WWM_REG ]}
+ - { id: 1, class: sgpr_64, preferred-register: $sgpr0_sgpr1 }
+ - { id: 2, class: sgpr_64, flags: [ ] }
+body: |
+ bb.0:
+ %2:sgpr_64 = COPY %1
+ %1:sgpr_64 = COPY %0
+...
>From 9a6e5925c909fe9207c5d66aed201589282c9b70 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Tue, 8 Oct 2024 06:24:11 +0000
Subject: [PATCH 5/7] AS
---
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index b23fea33183354..90000563393447 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1717,18 +1717,16 @@ bool GCNTargetMachine::parseMachineFunctionInfo(
}
auto setRegisterFlags = [&](const VRegInfo &Info) {
- for (const auto &Flag : Info.Flags) {
+ for (uint8_t Flag : Info.Flags) {
MFI->setFlag(Info.VReg, Flag);
}
};
- for (const auto &P : PFS.VRegInfosNamed) {
- const VRegInfo &Info = *P.second;
- setRegisterFlags(Info);
+ for (const auto &[_, Info] : PFS.VRegInfosNamed) {
+ setRegisterFlags(*Info);
}
- for (const auto &P : PFS.VRegInfos) {
- const VRegInfo &Info = *P.second;
- setRegisterFlags(Info);
+ for (const auto &[_, Info] : PFS.VRegInfos) {
+ setRegisterFlags(*Info);
}
auto parseAndCheckArgument = [&](const std::optional<yaml::SIArgument> &A,
>From c28f2f2a84375f362c5a428bd461733c552bf821 Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Tue, 8 Oct 2024 13:37:33 +0000
Subject: [PATCH 6/7] conditional
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index f2e2828850713d..890b551633380a 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -459,10 +459,8 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo {
unsigned SubReg) const;
std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override {
- if (Name == "WWM_REG") {
- return AMDGPU::VirtRegFlag::WWM_REG;
- }
- return {};
+ return (Name == "WWM_REG") ? AMDGPU::VirtRegFlag::WWM_REG
+ : std::optional<uint8_t>{};
}
SmallVector<SmallString<8>>
>From 79de29b2ab5d02826d6f4ee826d1f1238f56030c Mon Sep 17 00:00:00 2001
From: Akshat Oke <akshat....@amd.com>
Date: Wed, 9 Oct 2024 05:52:35 +0000
Subject: [PATCH 7/7] StringLiteral
---
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 6 +++---
llvm/lib/Target/AMDGPU/SIRegisterInfo.h | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ba29c574c2621e..f91d85eaa5f7a0 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -3852,13 +3852,13 @@ SIRegisterInfo::getSubRegAlignmentNumBits(const
TargetRegisterClass *RC,
return 0;
}
-SmallVector<SmallString<8>>
+SmallVector<StringLiteral>
SIRegisterInfo::getVRegFlagsOfReg(Register Reg,
const MachineFunction &MF) const {
- SmallVector<SmallString<8>> RegFlags;
+ SmallVector<StringLiteral> RegFlags;
const SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
if (FuncInfo->checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG)) {
- RegFlags.push_back(SmallString<8>("WWM_REG"));
+ RegFlags.push_back("WWM_REG");
}
return RegFlags;
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
index 890b551633380a..fe0b66f75bbaa2 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.h
@@ -459,11 +459,11 @@ class SIRegisterInfo final : public AMDGPUGenRegisterInfo
{
unsigned SubReg) const;
std::optional<uint8_t> getVRegFlagValue(StringRef Name) const override {
- return (Name == "WWM_REG") ? AMDGPU::VirtRegFlag::WWM_REG
- : std::optional<uint8_t>{};
+ return Name == "WWM_REG" ? AMDGPU::VirtRegFlag::WWM_REG
+ : std::optional<uint8_t>{};
}
- SmallVector<SmallString<8>>
+ SmallVector<StringLiteral>
getVRegFlagsOfReg(Register Reg, const MachineFunction &MF) const override;
};
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