================ @@ -0,0 +1,26 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 +# RUN: llc -mtriple=amdgcn -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s + +--- + +name: pre_allocate_wwm_regs_strict +tracksRegLiveness: true +body: | ---------------- arsenm wrote:
WWMSpills, SpillVGPRs, SpillPhysVGPRs, SGPRSpillsTo* https://github.com/llvm/llvm-project/pull/109963 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
