https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/109110
Backport 1825cf28dc83113200b623ebcf063eea35ade79a Requested by: @heiher >From 4d8867e154dfd99ae6d64de1d97f895c4a44d317 Mon Sep 17 00:00:00 2001 From: hev <wang...@loongson.cn> Date: Sat, 14 Sep 2024 11:19:34 +0800 Subject: [PATCH] [LoongArch][sanitizer] Fix SC_ADDRERR_{RD,WR} missing in the musl environment (#108557) Fixes #108550 (cherry picked from commit 1825cf28dc83113200b623ebcf063eea35ade79a) --- compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp index 648df0c4e5a760..b9b1f496df7c98 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_linux.cpp @@ -2014,6 +2014,18 @@ SignalContext::WriteFlag SignalContext::GetWriteFlag() const { return Unknown; return esr & ESR_ELx_WNR ? Write : Read; # elif defined(__loongarch__) + // In the musl environment, the Linux kernel uapi sigcontext.h is not + // included in signal.h. To avoid missing the SC_ADDRERR_{RD,WR} macros, + // copy them here. The LoongArch Linux kernel uapi is already stable, + // so there's no need to worry about the value changing. +# ifndef SC_ADDRERR_RD + // Address error was due to memory load +# define SC_ADDRERR_RD (1 << 30) +# endif +# ifndef SC_ADDRERR_WR + // Address error was due to memory store +# define SC_ADDRERR_WR (1 << 31) +# endif u32 flags = ucontext->uc_mcontext.__flags; if (flags & SC_ADDRERR_RD) return SignalContext::Read; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits