https://github.com/llvmbot created
https://github.com/llvm/llvm-project/pull/104823
Backport 05d17a1c705e1053f95b90aa37d91ce4f94a9287
Requested by: @davemgreen
>From 4de6aaf88b938e46291ed934211938fa3c17e9f6 Mon Sep 17 00:00:00 2001
From: David Green <david.gr...@arm.com>
Date: Mon, 19 Aug 2024 18:50:47 +0100
Subject: [PATCH] [GlobalISel] Bail out early for big-endian (#103310)
If we continue through the function we can currently hit crashes. We can
bail out early and fall back to SDAG.
Fixes #103032
(cherry picked from commit 05d17a1c705e1053f95b90aa37d91ce4f94a9287)
---
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 1 +
llvm/lib/Target/ARM/ARMCallLowering.cpp | 9 ++++++++
llvm/lib/Target/ARM/ARMCallLowering.h | 2 ++
.../AArch64/GlobalISel/endian_fallback.ll | 21 +++++++++++++++++++
.../ARM/GlobalISel/arm-irtranslator.ll | 2 +-
.../ARM/GlobalISel/arm-param-lowering.ll | 2 +-
6 files changed, 35 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/endian_fallback.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 68a8a273a1b479..eb010afd41b6b7 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -3889,6 +3889,7 @@ bool IRTranslator::runOnMachineFunction(MachineFunction
&CurMF) {
F.getSubprogram(), &F.getEntryBlock());
R << "unable to translate in big endian mode";
reportTranslationError(*MF, *TPC, *ORE, R);
+ return false;
}
// Release the per-function state when we return, whether we succeeded or
not.
diff --git a/llvm/lib/Target/ARM/ARMCallLowering.cpp
b/llvm/lib/Target/ARM/ARMCallLowering.cpp
index 9cc162d041f48b..883808ae981f5e 100644
--- a/llvm/lib/Target/ARM/ARMCallLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMCallLowering.cpp
@@ -50,6 +50,13 @@
using namespace llvm;
+// Whether Big-endian GISel is enabled, defaults to off, can be enabled for
+// testing.
+static cl::opt<bool>
+ EnableGISelBigEndian("enable-arm-gisel-bigendian", cl::Hidden,
+ cl::init(false),
+ cl::desc("Enable Global-ISel Big Endian Lowering"));
+
ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
: CallLowering(&TLI) {}
@@ -539,3 +546,5 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder
&MIRBuilder, CallLoweringInfo &
return true;
}
+
+bool ARMCallLowering::enableBigEndian() const { return EnableGISelBigEndian; }
\ No newline at end of file
diff --git a/llvm/lib/Target/ARM/ARMCallLowering.h
b/llvm/lib/Target/ARM/ARMCallLowering.h
index 38095617fb4f35..32c95a044d7b7e 100644
--- a/llvm/lib/Target/ARM/ARMCallLowering.h
+++ b/llvm/lib/Target/ARM/ARMCallLowering.h
@@ -42,6 +42,8 @@ class ARMCallLowering : public CallLowering {
bool lowerCall(MachineIRBuilder &MIRBuilder,
CallLoweringInfo &Info) const override;
+ bool enableBigEndian() const override;
+
private:
bool lowerReturnVal(MachineIRBuilder &MIRBuilder, const Value *Val,
ArrayRef<Register> VRegs,
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/endian_fallback.ll
b/llvm/test/CodeGen/AArch64/GlobalISel/endian_fallback.ll
new file mode 100644
index 00000000000000..6c27b4dd85f9b0
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/endian_fallback.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; RUN: llc -mtriple aarch64-unknown-linux-musl -O0 -global-isel-abort=2 < %s
2>&1 | FileCheck %s --check-prefix=CHECK-LE
+; RUN: llc -mtriple aarch64_be-unknown-linux-musl -O0 -global-isel-abort=2 <
%s 2>&1 | FileCheck %s --check-prefix=CHECK-BE
+
+; Make sure we fall-back to SDAG for BE targets.
+
+; CHECK-LE-NOT: warning: Instruction selection used fallback path for foo
+; CHECK-BE: warning: Instruction selection used fallback path for foo
+
+define <4 x i6> @foo(float %0, <4 x i6> %1) {
+; CHECK-LE-LABEL: foo:
+; CHECK-LE: // %bb.0:
+; CHECK-LE-NEXT: fmov d0, d1
+; CHECK-LE-NEXT: ret
+;
+; CHECK-BE-LABEL: foo:
+; CHECK-BE: // %bb.0:
+; CHECK-BE-NEXT: fmov d0, d1
+; CHECK-BE-NEXT: ret
+ ret <4 x i6> %1
+}
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
index 411cf78b621f8b..dc1d4b289c2ab8 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
@@ -1,5 +1,5 @@
; RUN: llc -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel
-stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
-check-prefix=CHECK -check-prefix=LITTLE
-; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel
-global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - |
FileCheck %s -check-prefix=CHECK -check-prefix=BIG
+; RUN: llc -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel
-global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator
-verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
-check-prefix=BIG
define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
index e8cd182196b622..65586f72c7c198 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll
@@ -1,5 +1,5 @@
; RUN: llc -O0 -mtriple arm-unknown -mattr=+vfp2,+v4t -global-isel
-stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
-check-prefix=CHECK -check-prefix=ARM -check-prefix=LITTLE
-; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel
-global-isel-abort=0 -stop-after=irtranslator -verify-machineinstrs %s -o - |
FileCheck %s -check-prefix=CHECK -check-prefix=ARM -check-prefix=BIG
+; RUN: llc -O0 -mtriple armeb-unknown -mattr=+vfp2,+v4t -global-isel
-global-isel-abort=0 -enable-arm-gisel-bigendian -stop-after=irtranslator
-verify-machineinstrs %s -o - | FileCheck %s -check-prefix=CHECK
-check-prefix=ARM -check-prefix=BIG
; RUN: llc -O0 -mtriple thumb-unknown -mattr=+vfp2,+v6t2 -global-isel
-stop-after=irtranslator -verify-machineinstrs %s -o - | FileCheck %s
-check-prefix=CHECK -check-prefix=LITTLE -check-prefix=THUMB
declare arm_aapcscc ptr @simple_reg_params_target(i32, ptr)
_______________________________________________
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
