=?utf-8?q?Björn?= Pettersson <bjorn.a.petters...@ericsson.com> Message-ID: In-Reply-To: <llvm.org/llvm/llvm-project/pull/89...@github.com>
llvmbot wrote: <!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-selectiondag Author: AtariDreams (AtariDreams) <details> <summary>Changes</summary> Cherry-picked from commits 5fd9bbdea6cc248469d5465de44e747378ffafcb and f9b419b7a038dcd51a7943b160acc867714c595f --- Full diff: https://github.com/llvm/llvm-project/pull/89766.diff 2 Files Affected: - (modified) llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (+8-1) - (modified) llvm/test/CodeGen/X86/shift-combine.ll (+35) ``````````diff diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index e806e0f0731f23..5038f8a1fc1562 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -9636,8 +9636,15 @@ static SDValue combineShiftOfShiftedLogic(SDNode *Shift, SelectionDAG &DAG) { if (ShiftAmtVal->getBitWidth() != C1Val.getBitWidth()) return false; + // The fold is not valid if the sum of the shift values doesn't fit in the + // given shift amount type. + bool Overflow = false; + APInt NewShiftAmt = C1Val.uadd_ov(*ShiftAmtVal, Overflow); + if (Overflow) + return false; + // The fold is not valid if the sum of the shift values exceeds bitwidth. - if ((*ShiftAmtVal + C1Val).uge(V.getScalarValueSizeInBits())) + if (NewShiftAmt.uge(V.getScalarValueSizeInBits())) return false; return true; diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll index cf45641fba6321..3316a332fafdff 100644 --- a/llvm/test/CodeGen/X86/shift-combine.ll +++ b/llvm/test/CodeGen/X86/shift-combine.ll @@ -787,3 +787,38 @@ define <4 x i32> @or_tree_with_mismatching_shifts_vec_i32(<4 x i32> %a, <4 x i32 %r = or <4 x i32> %or.ab, %or.cd ret <4 x i32> %r } + +; Reproducer for a DAGCombiner::combineShiftOfShiftedLogic bug. DAGCombiner +; need to check that the sum of the shift amounts fits in i8, which is the +; legal type used to described X86 shift amounts. Verify that we do not try to +; create a shift with 130+160 as shift amount, and verify that the stored +; value do not depend on %a1. +define void @combineShiftOfShiftedLogic(i128 %a1, i32 %a2, ptr %p) { +; X86-LABEL: combineShiftOfShiftedLogic: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %eax, 20(%ecx) +; X86-NEXT: movl $0, 16(%ecx) +; X86-NEXT: movl $0, 12(%ecx) +; X86-NEXT: movl $0, 8(%ecx) +; X86-NEXT: movl $0, 4(%ecx) +; X86-NEXT: movl $0, (%ecx) +; X86-NEXT: retl +; +; X64-LABEL: combineShiftOfShiftedLogic: +; X64: # %bb.0: +; X64-NEXT: # kill: def $edx killed $edx def $rdx +; X64-NEXT: shlq $32, %rdx +; X64-NEXT: movq %rdx, 16(%rcx) +; X64-NEXT: movq $0, 8(%rcx) +; X64-NEXT: movq $0, (%rcx) +; X64-NEXT: retq + %zext1 = zext i128 %a1 to i192 + %zext2 = zext i32 %a2 to i192 + %shl = shl i192 %zext1, 130 + %or = or i192 %shl, %zext2 + %res = shl i192 %or, 160 + store i192 %res, ptr %p, align 8 + ret void +} `````````` </details> https://github.com/llvm/llvm-project/pull/89766 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
