================ @@ -121,7 +121,12 @@ def HaswellPfmCounters : ProcPfmCounters { PfmIssueCounter<"HWPort7", "uops_executed_port:port_7"> ]; let ValidationCounters = [ - PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED"> + PfmValidationCounter<InstructionRetired, "INSTRUCTIONS_RETIRED">, + PfmValidationCounter<L1DCacheLoadMiss, "MEM_LOAD_UOPS_RETIRED:L1_MISS">, + PfmValidationCounter<L1ICacheLoadMiss, "L1-ICACHE-LOAD-MISSES">, + PfmValidationCounter<DataTLBLoadMiss, "DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK">, + PfmValidationCounter<DataTLBStoreMiss, "DTLB_STORE_MISSES:MISS_CAUSES_A_WALK">, + PfmValidationCounter<InstructionTLBLoadMiss, "ITLB_MISSES:MISS_CAUSES_A_WALK"> ]; ---------------- boomanaiden154 wrote:
Thanks for the suggestion! I've refactored everything into a default counters set that's split across AMD/Intel (as the counters between them differ). We might need to adapt as newer/older architectures are brought up, but this should be reasonably scalable. https://github.com/llvm/llvm-project/pull/76788 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits