Author: Freddy Ye Date: 2022-10-10T08:49:16+02:00 New Revision: bd5722b87b5aa1b8286762af7f29b6aae669dee1
URL: https://github.com/llvm/llvm-project/commit/bd5722b87b5aa1b8286762af7f29b6aae669dee1 DIFF: https://github.com/llvm/llvm-project/commit/bd5722b87b5aa1b8286762af7f29b6aae669dee1.diff LOG: [X86] Remove AVX512VP2INTERSECT from Sapphire Rapids. For more details, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html Reviewed By: pengfei Differential Revision: https://reviews.llvm.org/D135509 (cherry picked from commit 566c277c64f8f76d8911aa5fd931903a357ed7be) Added: Modified: llvm/lib/Support/X86TargetParser.cpp llvm/lib/Target/X86/X86.td Removed: ################################################################################ diff --git a/llvm/lib/Support/X86TargetParser.cpp b/llvm/lib/Support/X86TargetParser.cpp index 2567f3ed8034b..0daaa6d815bf0 100644 --- a/llvm/lib/Support/X86TargetParser.cpp +++ b/llvm/lib/Support/X86TargetParser.cpp @@ -203,10 +203,10 @@ constexpr FeatureBitset FeaturesTigerlake = FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; constexpr FeatureBitset FeaturesSapphireRapids = FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | - FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVX512VP2INTERSECT | - FeatureAVXVNNI | FeatureCLDEMOTE | FeatureENQCMD | FeatureMOVDIR64B | - FeatureMOVDIRI | FeaturePTWRITE | FeatureSERIALIZE | FeatureSHSTK | - FeatureTSXLDTRK | FeatureUINTR | FeatureWAITPKG; + FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE | + FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | + FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | + FeatureWAITPKG; // Intel Atom processors. // Bonnell has feature parity with Core2 and adds MOVBE. @@ -367,7 +367,7 @@ constexpr ProcInfo Processors[] = { // Tigerlake microarchitecture based processors. { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, // Sapphire Rapids microarchitecture based processors. - { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512VP2INTERSECT, FeaturesSapphireRapids }, + { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids }, // Alderlake microarchitecture based processors. { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, // Knights Landing processor. diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td index fa0a6bd415dc0..f98916e81cee9 100644 --- a/llvm/lib/Target/X86/X86.td +++ b/llvm/lib/Target/X86/X86.td @@ -909,7 +909,6 @@ def ProcessorFeatures { FeatureTSXLDTRK, FeatureENQCMD, FeatureSHSTK, - FeatureVP2INTERSECT, FeatureMOVDIRI, FeatureMOVDIR64B, FeatureUINTR]; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
