Author: jacquesguan Date: 2022-07-12T16:15:19+08:00 New Revision: 4d6d6e60c5b3f4d5c0d036925a0612703770b007
URL: https://github.com/llvm/llvm-project/commit/4d6d6e60c5b3f4d5c0d036925a0612703770b007 DIFF: https://github.com/llvm/llvm-project/commit/4d6d6e60c5b3f4d5c0d036925a0612703770b007.diff LOG: [RISCV][test] Precommit test for D129179. Differential Revision: https://reviews.llvm.org/D129463 Added: Modified: llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll index 49c46942c2632..7b5e0138410a5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll +++ b/llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll @@ -373,3 +373,57 @@ define void @masks() nounwind { %v8 = alloca <vscale x 8 x i1> ret void } + +define void @lmul_8_x5() nounwind { +; CHECK-LABEL: lmul_8_x5: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -80 +; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill +; CHECK-NEXT: addi s0, sp, 80 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: li a1, 40 +; CHECK-NEXT: mul a0, a0, a1 +; CHECK-NEXT: sub sp, sp, a0 +; CHECK-NEXT: andi sp, sp, -64 +; CHECK-NEXT: addi sp, s0, -80 +; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload +; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 80 +; CHECK-NEXT: ret + %v1 = alloca <vscale x 8 x i64> + %v2 = alloca <vscale x 8 x i64> + %v3 = alloca <vscale x 8 x i64> + %v4 = alloca <vscale x 8 x i64> + %v5 = alloca <vscale x 8 x i64> + ret void +} + +define void @lmul_8_x9() nounwind { +; CHECK-LABEL: lmul_8_x9: +; CHECK: # %bb.0: +; CHECK-NEXT: addi sp, sp, -80 +; CHECK-NEXT: sd ra, 72(sp) # 8-byte Folded Spill +; CHECK-NEXT: sd s0, 64(sp) # 8-byte Folded Spill +; CHECK-NEXT: addi s0, sp, 80 +; CHECK-NEXT: csrr a0, vlenb +; CHECK-NEXT: li a1, 72 +; CHECK-NEXT: mul a0, a0, a1 +; CHECK-NEXT: sub sp, sp, a0 +; CHECK-NEXT: andi sp, sp, -64 +; CHECK-NEXT: addi sp, s0, -80 +; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload +; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload +; CHECK-NEXT: addi sp, sp, 80 +; CHECK-NEXT: ret + %v1 = alloca <vscale x 8 x i64> + %v2 = alloca <vscale x 8 x i64> + %v3 = alloca <vscale x 8 x i64> + %v4 = alloca <vscale x 8 x i64> + %v5 = alloca <vscale x 8 x i64> + %v6 = alloca <vscale x 8 x i64> + %v7 = alloca <vscale x 8 x i64> + %v8 = alloca <vscale x 8 x i64> + %v9 = alloca <vscale x 8 x i64> + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
