Author: Albion Fung Date: 2021-06-21T21:06:23-05:00 New Revision: d723f268ae83cf1e107d1d3ecf5c415682495a75
URL: https://github.com/llvm/llvm-project/commit/d723f268ae83cf1e107d1d3ecf5c415682495a75 DIFF: https://github.com/llvm/llvm-project/commit/d723f268ae83cf1e107d1d3ecf5c415682495a75.diff LOG: Temp commit Added: Modified: clang/include/clang/Basic/BuiltinsPPC.def clang/lib/CodeGen/CGBuiltin.cpp clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c llvm/include/llvm/IR/IntrinsicsPowerPC.td llvm/lib/IR/Instructions.cpp llvm/lib/Target/PowerPC/PPCInstrPrefix.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/BuiltinsPPC.def b/clang/include/clang/Basic/BuiltinsPPC.def index 2a8643c770f68..67fcd39b85689 100644 --- a/clang/include/clang/Basic/BuiltinsPPC.def +++ b/clang/include/clang/Basic/BuiltinsPPC.def @@ -51,8 +51,8 @@ BUILTIN(__builtin_ppc_lharx, "isD*", "") BUILTIN(__builtin_ppc_lbarx, "UiUcD*", "") BUILTIN(__builtin_ppc_stdcx, "iLiD*Li", "") BUILTIN(__builtin_ppc_stwcx, "iiD*i", "") -BUILTIN(__builtin_ppc_sthcx, "isD*i", "") -BUILTIN(__builtin_ppc_stbcx, "icD*i", "") +BUILTIN(__builtin_ppc_sthcx, "isD*s", "") +BUILTIN(__builtin_ppc_stbcx, "icD*c", "") BUILTIN(__builtin_ppc_dcbtstt, "vv*s", "") BUILTIN(__builtin_ppc_dcbtt, "vv*c", "") BUILTIN(__builtin_ppc_mftbu, "Ui","") diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 1b30d44937f3e..2cf28f546a556 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -15342,6 +15342,18 @@ Value *CodeGenFunction::EmitPPCBuiltinExpr(unsigned BuiltinID, return Builder.CreateExtractElement(Unpacked, Index); } + case PPC::BI__builtin_ppc_sthcx: { + dbgs() << "GENNING CUSTOM SEXT:" << E->getNumArgs() <<"\n"; + // Value *Res = Builder.CreateSExt(Ops[1], Int32Ty); + Ops[1] = Builder.CreateSExt(Ops[1], Int32Ty); + llvm::Function *F = CGM.getIntrinsic(Intrinsic::ppc_sthcx); + // SmallVector<Value*, 2> NewOps; + // NewOps.push_back(Ops[0]); + // NewOps.push_back(Res); + // return Builder.CreateCall(F, NewOps); + return Builder.CreateCall(F, Ops); + } + // The PPC MMA builtins take a pointer to a __vector_quad as an argument. // Some of the MMA instructions accumulate their result into an existing // accumulator whereas the others generate a new accumulator. So we need to diff --git a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c index f4f02a01580f6..ba29d8986564c 100644 --- a/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c +++ b/clang/test/CodeGen/builtins-ppc-xlcompat-atomicLoadStore.c @@ -1,72 +1,76 @@ -// RUN: %clang -mcpu=pwr8 -c -m32 -O2 -S %s -o - | \ -// RUN: FileCheck %s --check-prefix=CHECK-32 -// RUN: %clang -mcpu=pwr8 -c -m64 -O2 -S %s -o - | \ -// RUN: FileCheck %s --check-prefix=CHECK-64 +// RUN: %clang_cc1 -triple=powerpc-unknown-aix -O2 -S %s -o - | \ +// RUN: FileCheck %s --check-prefix=CHECK-AIX +// RUN: %clang_cc1 -triple=powerpc64-unknown-aix -O2 -S %s -o - | \ +// RUN: FileCheck %s --check-prefix=CHECK-AIX +// RUN: %clang_cc1 -triple=powerpc64le-unknown-unknown -O2 -S %s \ +// RUN: -o - | FileCheck %s --check-prefix=CHECK-COMMON +// RUN: %clang_cc1 -triple=powerpc64be-unknown-unknown -O2 -S %s \ +// RUN: -o - | FileCheck %s --check-prefix=CHECK-COMMON int test_lwarx(volatile int* a) { - // CHECK-64-LABEL: test_lwarx - // CHECK-64: lwarx 3, 0, 3 - // CHECK-64-NEXT: extsw 3, 3 - // CHECK-64-NEXT: blr + // CHECK-COMMON-LABEL: test_lwarx + // CHECK-COMMON: lwarx 3, 0, 3 + // CHECK-COMMON-NEXT: extsw 3, 3 + // CHECK-COMMON-NEXT: blr - // CHECK-32-LABEL: test_lwarx - // CHECK-32: lwarx 3, 0, 3 - // CHECK-32-NEXT: blr + // CHECK-AIX-LABEL: test_lwarx + // CHECK-AIX: lwarx 3, 0, 3 + // CHECK-AIX-NEXT: blr return __lwarx(a); } short test_lharx(volatile short* a) { - // CHECK-64-LABEL: test_lharx - // CHECK-64: lharx 3, 0, 3 - // CHECK-64-NEXT: extsh 3, 3 - // CHECK-64-NEXT: blr + // CHECK-COMMON-LABEL: test_lharx + // CHECK-COMMON: lharx 3, 0, 3 + // CHECK-COMMON-NEXT: extsh 3, 3 + // CHECK-COMMON-NEXT: blr - // CHECK-32-LABEL: test_lharx - // CHECK-32: lharx 3, 0, 3 - // CHECK-32-NEXT: extsh 3, 3 - // CHECK-32-NEXT: blr + // CHECK-AIX-LABEL: test_lharx + // CHECK-AIX: lharx 3, 0, 3 + // CHECK-AIX-NEXT: extsh 3, 3 + // CHECK-AIX-NEXT: blr return __lharx(a); } char test_lbarx(volatile unsigned char* a) { - // CHECK-64-LABEL: test_lbarx - // CHECK-64: lbarx 3, 0, 3 - // CHECK-64-NEXT: clrldi 3, 3, 56 - // CHECK-64-NEXT: blr + // CHECK-COMMON-LABEL: test_lbarx + // CHECK-COMMON: lbarx 3, 0, 3 + // CHECK-COMMON-NEXT: clrldi 3, 3, 56 + // CHECK-COMMON-NEXT: blr - // CHECK-32-LABEL: test_lbarx - // CHECK-32: lbarx 3, 0, 3 - // CHECK-32-NEXT: clrlwi 3, 3, 24 - // CHECK-32-NEXT: blr + // CHECK-AIX-LABEL: test_lbarx + // CHECK-AIX: lbarx 3, 0, 3 + // CHECK-AIX-NEXT: extsb 3, 3 + // CHECK-AIX-NEXT: blr return __lbarx(a); } int test_stwcx(volatile int* a, int val) { - // CHECK-64-LABEL: test_stwcx - // CHECK-64: stwcx. 4, 0, 3 + // CHECK-COMMON-LABEL: test_stwcx + // CHECK-COMMON: stwcx. 4, 0, 3 - // CHECK-32-LABEL: test_stwcx - // CHECK-32: stwcx. 4, 0, 3 + // CHECK-AIX-LABEL: test_stwcx + // CHECK-AIX: stwcx. 4, 0, 3 return __stwcx(a, val); } int test_sthcx(volatile short* a, short val) { - // CHECK-64-LABEL: test_sthcx - // CHECK-64: sthcx. 4, 0, 3 + // CHECK-COMMON-LABEL: test_sthcx + // CHECK-COMMON: sthcx. 4, 0, 3 - // CHECK-32-LABEL: test_sthcx - // CHECK-32: sthcx. 4, 0, 3 + // CHECK-AIX-LABEL: test_sthcx + // CHECK-AIX: sthcx. 4, 0, 3 return __sthcx(a, val); } int test_stbcx(volatile char* a, char val) { - // CHECK-64-LABEL: test_stbcx - // CHECK-64: stbcx. 4, 0, 3 + // CHECK-COMMON-LABEL: test_stbcx + // CHECK-COMMON: stbcx. 4, 0, 3 - // CHECK-32-LABEL: test_stbcx - // CHECK-32: stbcx. 4, 0, 3 + // CHECK-AIX-LABEL: test_stbcx + // CHECK-AIX: stbcx. 4, 0, 3 return __stbcx(a, val); } diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td index ea5ca61815007..fc20f220894e4 100644 --- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td +++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td @@ -1535,9 +1535,9 @@ let TargetPrefix = "ppc" in { Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i64_ty], [IntrWriteMem]>; def int_ppc_stwcx : GCCBuiltin<"__builtin_ppc_stwcx">, Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; - def int_ppc_sthcx : GCCBuiltin<"__builtin_ppc_sthcx">, + def int_ppc_sthcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; - def int_ppc_stbcx : GCCBuiltin<"__builtin_ppc_stbcx">, + def int_ppc_stbcx : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty, llvm_i32_ty], [IntrWriteMem]>; } diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index f2316b6091930..eb3bb8367759d 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -2936,6 +2936,8 @@ unsigned CastInst::isEliminableCastPair( CastInst *CastInst::Create(Instruction::CastOps op, Value *S, Type *Ty, const Twine &Name, Instruction *InsertBefore) { + dbgs() << "Op code bitcast: " << BitCast << "\n"; + dbgs() << "DEBUG CREATE BEFORE: " << op << " NEXT " << *S << " TYPE " << *Ty << "\n"; assert(castIsValid(op, S, Ty) && "Invalid cast!"); // Construct and return the appropriate CastInst subclass switch (op) { diff --git a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td index 6f3f557cead09..8d544f6c1040f 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrPrefix.td +++ b/llvm/lib/Target/PowerPC/PPCInstrPrefix.td @@ -2849,9 +2849,9 @@ def : Pat<(int_ppc_lharx xoaddr:$dst), (LHARX xoaddr:$dst)>; def : Pat<(int_ppc_lbarx xoaddr:$dst), (LBARX xoaddr:$dst)>; -def : Pat<(int_ppc_stwcx xoaddr:$dst, gprc:$A), - (STWCX gprc:$A, xoaddr:$dst)>; -def : Pat<(int_ppc_sthcx xoaddr:$dst, gprc:$A), - (STHCX gprc:$A, xoaddr:$dst)>; +// def : Pat<(int_ppc_stwcx xoaddr:$dst, gprc:$A), + // (STWCX gprc:$A, xoaddr:$dst)>; +def : Pat<(int_ppc_sthcx xoaddr:$dst, (sextloadi32 gprc:$A)), + (STHCX (EXTSH gprc:$A), xoaddr:$dst)>; def : Pat<(int_ppc_stbcx xoaddr:$dst, gprc:$A), - (STBCX gprc:$A, xoaddr:$dst)>; + (STBCX (EXTSB gprc:$A), xoaddr:$dst)>; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
