Author: Craig Topper Date: 2021-01-22T14:51:22-08:00 New Revision: d65e8ee507f82ddca018267d0ce627518dd07337
URL: https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337 DIFF: https://github.com/llvm/llvm-project/commit/d65e8ee507f82ddca018267d0ce627518dd07337.diff LOG: [RISCV] Add more cmov isel patterns to handle seteq/ne with a small non-zero immediate. Similar to our free standing setcc patterns, we can use ADDI to subtract the immediate from the other operand. Then the cmov can check if the result is zero or non-zero. Reviewed By: mundaym Differential Revision: https://reviews.llvm.org/D95169 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td llvm/test/CodeGen/RISCV/select-optimize-multiple.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index d4ba4f8e285c..f075699c17f0 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -778,10 +778,15 @@ def : Pat<(riscv_grevi GPR:$rs1, (i64 56)), (REV8_RV64 GPR:$rs1)>; let Predicates = [HasStdExtZbt] in { def : Pat<(or (and (not GPR:$rs2), GPR:$rs3), (and GPR:$rs2, GPR:$rs1)), (CMIX GPR:$rs1, GPR:$rs2, GPR:$rs3)>; + def : Pat<(select (XLenVT (setne GPR:$rs2, 0)), GPR:$rs1, GPR:$rs3), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; def : Pat<(select (XLenVT (seteq GPR:$rs2, 0)), GPR:$rs3, GPR:$rs1), (CMOV GPR:$rs1, GPR:$rs2, GPR:$rs3)>; +def : Pat<(select (XLenVT (setne GPR:$x, simm12_plus1:$y)), GPR:$rs1, GPR:$rs3), + (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; +def : Pat<(select (XLenVT (seteq GPR:$x, simm12_plus1:$y)), GPR:$rs3, GPR:$rs1), + (CMOV GPR:$rs1, (ADDI GPR:$x, (NegImm simm12_plus1:$y)), GPR:$rs3)>; def : Pat<(select (XLenVT (setne GPR:$x, GPR:$y)), GPR:$rs1, GPR:$rs3), (CMOV GPR:$rs1, (XOR GPR:$x, GPR:$y), GPR:$rs3)>; def : Pat<(select (XLenVT (seteq GPR:$x, GPR:$y)), GPR:$rs3, GPR:$rs1), diff --git a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll index b6ecf3930b24..2b7f275bf6d6 100644 --- a/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll +++ b/llvm/test/CodeGen/RISCV/select-optimize-multiple.ll @@ -27,8 +27,7 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind { ; ; RV32IBT-LABEL: cmovcc64: ; RV32IBT: # %bb.0: # %entry -; RV32IBT-NEXT: addi a5, zero, 123 -; RV32IBT-NEXT: xor a5, a0, a5 +; RV32IBT-NEXT: addi a5, a0, -123 ; RV32IBT-NEXT: cmov a0, a5, a3, a1 ; RV32IBT-NEXT: cmov a1, a5, a4, a2 ; RV32IBT-NEXT: ret @@ -45,8 +44,7 @@ define i64 @cmovcc64(i32 signext %a, i64 %b, i64 %c) nounwind { ; ; RV64IBT-LABEL: cmovcc64: ; RV64IBT: # %bb.0: # %entry -; RV64IBT-NEXT: addi a3, zero, 123 -; RV64IBT-NEXT: xor a0, a0, a3 +; RV64IBT-NEXT: addi a0, a0, -123 ; RV64IBT-NEXT: cmov a0, a0, a2, a1 ; RV64IBT-NEXT: ret entry: @@ -133,8 +131,7 @@ define i128 @cmovcc128(i64 signext %a, i128 %b, i128 %c) nounwind { ; ; RV64IBT-LABEL: cmovcc128: ; RV64IBT: # %bb.0: # %entry -; RV64IBT-NEXT: addi a5, zero, 123 -; RV64IBT-NEXT: xor a5, a0, a5 +; RV64IBT-NEXT: addi a5, a0, -123 ; RV64IBT-NEXT: cmov a0, a5, a3, a1 ; RV64IBT-NEXT: cmov a1, a5, a4, a2 ; RV64IBT-NEXT: ret @@ -434,8 +431,7 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind { ; ; RV32IBT-LABEL: cmovccdep: ; RV32IBT: # %bb.0: # %entry -; RV32IBT-NEXT: addi a4, zero, 123 -; RV32IBT-NEXT: xor a0, a0, a4 +; RV32IBT-NEXT: addi a0, a0, -123 ; RV32IBT-NEXT: cmov a1, a0, a2, a1 ; RV32IBT-NEXT: cmov a0, a0, a3, a1 ; RV32IBT-NEXT: add a0, a1, a0 @@ -462,8 +458,7 @@ define i32 @cmovccdep(i32 signext %a, i32 %b, i32 %c, i32 %d) nounwind { ; ; RV64IBT-LABEL: cmovccdep: ; RV64IBT: # %bb.0: # %entry -; RV64IBT-NEXT: addi a4, zero, 123 -; RV64IBT-NEXT: xor a0, a0, a4 +; RV64IBT-NEXT: addi a0, a0, -123 ; RV64IBT-NEXT: cmov a1, a0, a2, a1 ; RV64IBT-NEXT: cmov a0, a0, a3, a1 ; RV64IBT-NEXT: addw a0, a1, a0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
