Author: Craig Topper Date: 2021-01-22T12:49:10-08:00 New Revision: d985c7321f0b9cbaf8f8423a7faa645bb5966fc8
URL: https://github.com/llvm/llvm-project/commit/d985c7321f0b9cbaf8f8423a7faa645bb5966fc8 DIFF: https://github.com/llvm/llvm-project/commit/d985c7321f0b9cbaf8f8423a7faa645bb5966fc8.diff LOG: [RISCV] Swap encodings of max and minu to match 0.93 bitmanip spec. Reviewed By: asb, frasercrmck Differential Revision: https://reviews.llvm.org/D94580 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfoB.td llvm/test/MC/RISCV/rv32zbb-valid.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td index 91d325942f9c..5ad8fc2b4636 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoB.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoB.td @@ -333,8 +333,8 @@ def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh">, Sched<[]>; let Predicates = [HasStdExtZbb] in { def MIN : ALU_rr<0b0000101, 0b100, "min">, Sched<[]>; -def MAX : ALU_rr<0b0000101, 0b101, "max">, Sched<[]>; -def MINU : ALU_rr<0b0000101, 0b110, "minu">, Sched<[]>; +def MINU : ALU_rr<0b0000101, 0b101, "minu">, Sched<[]>; +def MAX : ALU_rr<0b0000101, 0b110, "max">, Sched<[]>; def MAXU : ALU_rr<0b0000101, 0b111, "maxu">, Sched<[]>; } // Predicates = [HasStdExtZbb] diff --git a/llvm/test/MC/RISCV/rv32zbb-valid.s b/llvm/test/MC/RISCV/rv32zbb-valid.s index dff8364fea94..13cf4a1bf9bd 100644 --- a/llvm/test/MC/RISCV/rv32zbb-valid.s +++ b/llvm/test/MC/RISCV/rv32zbb-valid.s @@ -42,12 +42,12 @@ sext.h t0, t1 # CHECK-ASM-AND-OBJ: min t0, t1, t2 # CHECK-ASM: encoding: [0xb3,0x42,0x73,0x0a] min t0, t1, t2 -# CHECK-ASM-AND-OBJ: max t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a] -max t0, t1, t2 # CHECK-ASM-AND-OBJ: minu t0, t1, t2 -# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a] +# CHECK-ASM: encoding: [0xb3,0x52,0x73,0x0a] minu t0, t1, t2 +# CHECK-ASM-AND-OBJ: max t0, t1, t2 +# CHECK-ASM: encoding: [0xb3,0x62,0x73,0x0a] +max t0, t1, t2 # CHECK-ASM-AND-OBJ: maxu t0, t1, t2 # CHECK-ASM: encoding: [0xb3,0x72,0x73,0x0a] maxu t0, t1, t2 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
