Author: Hsiangkai Wang Date: 2021-01-22T00:47:32+08:00 New Revision: 9dd5aea1e0397f693a739bffb03fd94dc8e1ec79
URL: https://github.com/llvm/llvm-project/commit/9dd5aea1e0397f693a739bffb03fd94dc8e1ec79 DIFF: https://github.com/llvm/llvm-project/commit/9dd5aea1e0397f693a739bffb03fd94dc8e1ec79.diff LOG: [RISCV] Make LMUL field in VTYPE continuous. Upgrade RISC-V V extension to v1.0-08a0b46. Update the VTYPE encoding. Make LMUL encoding in a continuous field. Added: Modified: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll llvm/test/MC/RISCV/rvv/snippet.s llvm/test/MC/RISCV/rvv/vsetvl.s Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index cd81e5a07975..6c9f860c204c 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -353,17 +353,13 @@ inline static bool isValidLMUL(unsigned LMUL, bool Fractional) { // -----+------------+------------------------------------------------ // 7 | vma | Vector mask agnostic // 6 | vta | Vector tail agnostic -// 5 | vlmul[2] | Fractional lmul? -// 4:2 | vsew[2:0] | Standard element width (SEW) setting -// 1:0 | vlmul[1:0] | Vector register group multiplier (LMUL) setting -// -// TODO: This format will change for the V extensions spec v1.0. +// 5:3 | vsew[2:0] | Standard element width (SEW) setting +// 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW, bool TailAgnostic, bool MaskAgnostic) { unsigned VLMULBits = static_cast<unsigned>(VLMUL); unsigned VSEWBits = static_cast<unsigned>(VSEW); - unsigned VTypeI = - ((VLMULBits & 0x4) << 3) | (VSEWBits << 2) | (VLMULBits & 0x3); + unsigned VTypeI = (VSEWBits << 3) | (VLMULBits & 0x7); if (TailAgnostic) VTypeI |= 0x40; if (MaskAgnostic) @@ -372,14 +368,13 @@ inline static unsigned encodeVTYPE(RISCVVLMUL VLMUL, RISCVVSEW VSEW, return VTypeI; } -// TODO: This format will change for the V extensions spec v1.0. inline static RISCVVLMUL getVLMUL(unsigned VType) { - unsigned VLMUL = (VType & 0x3) | ((VType & 0x20) >> 3); + unsigned VLMUL = VType & 0x7; return static_cast<RISCVVLMUL>(VLMUL); } inline static RISCVVSEW getVSEW(unsigned VType) { - unsigned VSEW = (VType >> 2) & 0x7; + unsigned VSEW = (VType >> 3) & 0x7; return static_cast<RISCVVSEW>(VSEW); } diff --git a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir index f323bf1b3161..a93ec2c55cb8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir +++ b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir @@ -39,13 +39,13 @@ body: | # POST-INSERTER: %1:gpr = COPY $x12 # POST-INSERTER: %2:gpr = COPY $x11 # POST-INSERTER: %3:gpr = COPY $x10 -# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %7:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype # POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) -# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %8:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype # POST-INSERTER: %5:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %9:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype # POST-INSERTER: %6:vr = PseudoVADD_VV_M1 killed %4, killed %5, $noreg, -1, implicit $vl, implicit $vtype -# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 76, implicit-def $vl, implicit-def $vtype +# POST-INSERTER: dead %10:gpr = PseudoVSETVLI %0, 88, implicit-def $vl, implicit-def $vtype # POST-INSERTER: PseudoVSE64_V_M1 killed %6, %3, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) # CODEGEN: vsetvli a3, a3, e64,m1,ta,mu diff --git a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll index 53f316f61e92..eec35b114e79 100644 --- a/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll +++ b/llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll @@ -25,11 +25,11 @@ define void @vadd_vint64m1( ; PRE-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $x0, 64, implicit $vl, implicit $vtype ; PRE-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $x0, 64, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) -; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %6:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %3:vr = PseudoVLE64_V_M1 %1, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pa, align 8) -; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %7:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %4:vr = PseudoVLE64_V_M1 %2, $noreg, -1, implicit $vl, implicit $vtype :: (load unknown-size from %ir.pb, align 8) -; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %8:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: %5:vr = PseudoVADD_VV_M1 killed %3, killed %4, $noreg, -1, implicit $vl, implicit $vtype -; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 76, implicit-def $vl, implicit-def $vtype +; POST-INSERTER: dead %9:gpr = PseudoVSETVLI $x0, 88, implicit-def $vl, implicit-def $vtype ; POST-INSERTER: PseudoVSE64_V_M1 killed %5, %0, $noreg, -1, implicit $vl, implicit $vtype :: (store unknown-size into %ir.pc, align 8) diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s index 94e9b5fe9da5..f0f89c0c3b11 100644 --- a/llvm/test/MC/RISCV/rvv/snippet.s +++ b/llvm/test/MC/RISCV/rvv/snippet.s @@ -6,7 +6,7 @@ loop: vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors -# CHECK-INST: d7 76 65 0c vsetvli a3, a0, e16,m4,ta,ma +# CHECK-INST: d7 76 a5 0c vsetvli a3, a0, e16,m4,ta,ma vle16.v v4, (a1) # Get 16b vector # CHECK-INST: 07 d2 05 02 vle16.v v4, (a1) slli t1, a3, 1 # Multiply length by two bytes/element @@ -17,7 +17,7 @@ loop: # CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0 vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values -# CHECK-INST: 57 70 b5 0c vsetvli zero, a0, e32,m8,ta,ma +# CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32,m8,ta,ma vsrl.vi v8, v8, 3 # CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3 vse32.v v8, (a2) # Store vector of 32b diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s index 351d3febdf03..c32126b0e24f 100644 --- a/llvm/test/MC/RISCV/rvv/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -10,69 +10,69 @@ vsetvli a2, a0, e32,m1,ta,ma # CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma -# CHECK-ENCODING: [0x57,0x76,0x85,0x0c] +# CHECK-ENCODING: [0x57,0x76,0x05,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 85 0c <unknown> +# CHECK-UNKNOWN: 57 76 05 0d <unknown> vsetvli a2, a0, e32,m2,ta,ma # CHECK-INST: vsetvli a2, a0, e32,m2,ta,ma -# CHECK-ENCODING: [0x57,0x76,0x95,0x0c] +# CHECK-ENCODING: [0x57,0x76,0x15,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 95 0c <unknown> +# CHECK-UNKNOWN: 57 76 15 0d <unknown> vsetvli a2, a0, e32,m4,ta,ma # CHECK-INST: vsetvli a2, a0, e32,m4,ta,ma -# CHECK-ENCODING: [0x57,0x76,0xa5,0x0c] +# CHECK-ENCODING: [0x57,0x76,0x25,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 a5 0c <unknown> +# CHECK-UNKNOWN: 57 76 25 0d <unknown> vsetvli a2, a0, e32,m8,ta,ma # CHECK-INST: vsetvli a2, a0, e32,m8,ta,ma -# CHECK-ENCODING: [0x57,0x76,0xb5,0x0c] +# CHECK-ENCODING: [0x57,0x76,0x35,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 b5 0c <unknown> +# CHECK-UNKNOWN: 57 76 35 0d <unknown> vsetvli a2, a0, e32,mf2,ta,ma # CHECK-INST: vsetvli a2, a0, e32,mf2,ta,ma -# CHECK-ENCODING: [0x57,0x76,0xb5,0x0e] +# CHECK-ENCODING: [0x57,0x76,0x75,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 b5 0e <unknown> +# CHECK-UNKNOWN: 57 76 75 0d <unknown> vsetvli a2, a0, e32,mf4,ta,ma # CHECK-INST: vsetvli a2, a0, e32,mf4,ta,ma -# CHECK-ENCODING: [0x57,0x76,0xa5,0x0e] +# CHECK-ENCODING: [0x57,0x76,0x65,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 a5 0e <unknown> +# CHECK-UNKNOWN: 57 76 65 0d <unknown> vsetvli a2, a0, e32,mf8,ta,ma # CHECK-INST: vsetvli a2, a0, e32,mf8,ta,ma -# CHECK-ENCODING: [0x57,0x76,0x95,0x0e] +# CHECK-ENCODING: [0x57,0x76,0x55,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 95 0e <unknown> +# CHECK-UNKNOWN: 57 76 55 0d <unknown> vsetvli a2, a0, e32,m1,ta,ma # CHECK-INST: vsetvli a2, a0, e32,m1,ta,ma -# CHECK-ENCODING: [0x57,0x76,0x85,0x0c] +# CHECK-ENCODING: [0x57,0x76,0x05,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 85 0c <unknown> +# CHECK-UNKNOWN: 57 76 05 0d <unknown> vsetvli a2, a0, e32,m1,tu,ma # CHECK-INST: vsetvli a2, a0, e32,m1,tu,ma -# CHECK-ENCODING: [0x57,0x76,0x85,0x08] +# CHECK-ENCODING: [0x57,0x76,0x05,0x09] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 85 08 <unknown> +# CHECK-UNKNOWN: 57 76 05 09 <unknown> vsetvli a2, a0, e32,m1,ta,mu # CHECK-INST: vsetvli a2, a0, e32,m1,ta,mu -# CHECK-ENCODING: [0x57,0x76,0x85,0x04] +# CHECK-ENCODING: [0x57,0x76,0x05,0x05] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 85 04 <unknown> +# CHECK-UNKNOWN: 57 76 05 05 <unknown> vsetvli a2, a0, e32,m1,tu,mu # CHECK-INST: vsetvli a2, a0, e32,m1 -# CHECK-ENCODING: [0x57,0x76,0x85,0x00] +# CHECK-ENCODING: [0x57,0x76,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions) -# CHECK-UNKNOWN: 57 76 85 00 <unknown> +# CHECK-UNKNOWN: 57 76 05 01 <unknown> vsetvl a2, a0, a1 # CHECK-INST: vsetvl a2, a0, a1 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
