Author: Simon Pilgrim Date: 2021-01-19T11:04:13Z New Revision: 5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406
URL: https://github.com/llvm/llvm-project/commit/5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406 DIFF: https://github.com/llvm/llvm-project/commit/5626adcd6bbaadd12fe5bf15cd2d39ece2e5c406.diff LOG: [X86][SSE] combineVectorSignBitsTruncation - fold trunc(srl(x,c)) -> packss(sra(x,c)) If a srl doesn't introduce any sign bits into the truncated result, then replace with a sra to let us use a PACKSS truncation - fixes a regression noticed in D56387 on pre-SSE41 targets that don't have PACKUSDW. Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp llvm/test/CodeGen/X86/vector-trunc.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 97fcef0b92fa..0ee671710219 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -46071,9 +46071,23 @@ static SDValue combineVectorSignBitsTruncation(SDNode *N, const SDLoc &DL, if (SVT == MVT::i32 && NumSignBits != InSVT.getSizeInBits()) return SDValue(); - if (NumSignBits > (InSVT.getSizeInBits() - NumPackedSignBits)) + unsigned MinSignBits = InSVT.getSizeInBits() - NumPackedSignBits; + if (NumSignBits > MinSignBits) return truncateVectorWithPACK(X86ISD::PACKSS, VT, In, DL, DAG, Subtarget); + // If we have a srl that only generates signbits that we will discard in + // the truncation then we can use PACKSS by converting the srl to a sra. + // SimplifyDemandedBits often relaxes sra to srl so we need to reverse it. + if (In.getOpcode() == ISD::SRL && N->isOnlyUserOf(In.getNode())) + if (const APInt *ShAmt = DAG.getValidShiftAmountConstant( + In, APInt::getAllOnesValue(VT.getVectorNumElements()))) { + if (*ShAmt == MinSignBits) { + SDValue NewIn = DAG.getNode(ISD::SRA, DL, InVT, In->ops()); + return truncateVectorWithPACK(X86ISD::PACKSS, VT, NewIn, DL, DAG, + Subtarget); + } + } + return SDValue(); } diff --git a/llvm/test/CodeGen/X86/vector-trunc.ll b/llvm/test/CodeGen/X86/vector-trunc.ll index f35e315bbb0b..1d8d6f66521e 100644 --- a/llvm/test/CodeGen/X86/vector-trunc.ll +++ b/llvm/test/CodeGen/X86/vector-trunc.ll @@ -452,10 +452,9 @@ define <8 x i16> @trunc8i32_8i16_lshr(<8 x i32> %a) { ; ; SSSE3-LABEL: trunc8i32_8i16_lshr: ; SSSE3: # %bb.0: # %entry -; SSSE3-NEXT: movdqa {{.*#+}} xmm2 = [2,3,6,7,10,11,14,15,10,11,14,15,14,15,128,128] -; SSSE3-NEXT: pshufb %xmm2, %xmm1 -; SSSE3-NEXT: pshufb %xmm2, %xmm0 -; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSSE3-NEXT: psrad $16, %xmm1 +; SSSE3-NEXT: psrad $16, %xmm0 +; SSSE3-NEXT: packssdw %xmm1, %xmm0 ; SSSE3-NEXT: retq ; ; SSE41-LABEL: trunc8i32_8i16_lshr: _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
