Author: Bjorn Pettersson Date: 2021-01-16T14:33:19+01:00 New Revision: 4f155567317d3187bc18be866b3f3b5352f1bfa5
URL: https://github.com/llvm/llvm-project/commit/4f155567317d3187bc18be866b3f3b5352f1bfa5 DIFF: https://github.com/llvm/llvm-project/commit/4f155567317d3187bc18be866b3f3b5352f1bfa5.diff LOG: [LegalizeDAG] Handle NeedInvert when expanding BR_CC This is a follow-up fix to commit 03c8d6a0c4bd0016bdfd1e5. Seems like we now end up with NeedInvert being set in the result from LegalizeSetCCCondCode more often than in the past, so we need to handle NeedInvert when expanding BR_CC. Not sure how to deal with the "Tmp4.getNode()" case properly, but current assumption is that that code path isn't impacted by the changes in 03c8d6a0c4bd0016bdfd1e5 so we can simply move the old assert into the if-branch and only handle NeedInvert in the else-branch. I think that the test case added here, for PowerPC, might have failed also before commit 03c8d6a0c4bd0016bdfd1e5. But we started to hit the assert more often downstream when having merged that commit. Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D94762 Added: llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll Modified: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Removed: ################################################################################ diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 2437b07e7d0e..2ef3d9947169 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3966,16 +3966,16 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { (void)Legalized; assert(Legalized && "Can't legalize BR_CC with legal condition!"); - assert(!NeedInvert && "Don't know how to invert BR_CC!"); - // If we expanded the SETCC by swapping LHS and RHS, create a new BR_CC // node. if (Tmp4.getNode()) { + assert(!NeedInvert && "Don't know how to invert BR_CC!"); + Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, Tmp3, Node->getOperand(4)); } else { Tmp3 = DAG.getConstant(0, dl, Tmp2.getValueType()); - Tmp4 = DAG.getCondCode(ISD::SETNE); + Tmp4 = DAG.getCondCode(NeedInvert ? ISD::SETEQ : ISD::SETNE); Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, Tmp3, Node->getOperand(4)); } diff --git a/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll new file mode 100644 index 000000000000..1e109d0ea4a7 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/legalize-invert-br_cc.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -O1 -mtriple powerpc -mattr=+spe -o - %s | FileCheck %s + +; This used to hit an assert +; +; ../lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:3971: bool {anonymous}::SelectionDAGLegalize::ExpandNode(llvm::SDNode*): Assertion `!NeedInvert && "Don't know how to invert BR_CC!"' failed. + +define void @test_fcmpueq_legalize_br_cc_with_invert(float %a) { +; CHECK-LABEL: test_fcmpueq_legalize_br_cc_with_invert: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: lis 4, .LCPI0_0@ha +; CHECK-NEXT: lwz 4, .LCPI0_0@l(4) +; CHECK-NEXT: .LBB0_1: # %l1 +; CHECK-NEXT: # +; CHECK-NEXT: efscmplt 7, 3, 4 +; CHECK-NEXT: efscmpgt 0, 3, 4 +; CHECK-NEXT: mfcr 5 # cr7 +; CHECK-NEXT: mcrf 7, 0 +; CHECK-NEXT: mfcr 6 # cr7 +; CHECK-NEXT: rlwinm 5, 5, 30, 31, 31 +; CHECK-NEXT: rlwinm 6, 6, 30, 31, 31 +; CHECK-NEXT: or. 5, 6, 5 +; CHECK-NEXT: beq 0, .LBB0_1 +; CHECK-NEXT: # %bb.2: # %l2 +; CHECK-NEXT: blr +entry: + br label %l1 +l1: + %fcmp = fcmp ueq float %a, 0xC6306B3440000000 + br i1 %fcmp, label %l1, label %l2 +l2: + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
