Author: Craig Topper
Date: 2021-01-15T09:09:35-08:00
New Revision: 4c5066b0789d9c38d6362a684346b68261911d29

URL: 
https://github.com/llvm/llvm-project/commit/4c5066b0789d9c38d6362a684346b68261911d29
DIFF: 
https://github.com/llvm/llvm-project/commit/4c5066b0789d9c38d6362a684346b68261911d29.diff

LOG: [TargetLowering] Don't speculatively call ComputeNumSignBits. NFC

These methods are recursive so a little costly.

We only look at the result in one place in this function and it's
conditional. We also only need the second call if the first had
enough returned enough sign bits.

Added: 
    

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp 
b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 6ae0a39962b33..21953373b745a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -6092,8 +6092,6 @@ bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT 
VT, const SDLoc &dl,
 
   unsigned OuterBitSize = VT.getScalarSizeInBits();
   unsigned InnerBitSize = HiLoVT.getScalarSizeInBits();
-  unsigned LHSSB = DAG.ComputeNumSignBits(LHS);
-  unsigned RHSSB = DAG.ComputeNumSignBits(RHS);
 
   // LL, LH, RL, and RH must be either all NULL or all set to a value.
   assert((LL.getNode() && LH.getNode() && RL.getNode() && RH.getNode()) ||
@@ -6142,8 +6140,9 @@ bool TargetLowering::expandMUL_LOHI(unsigned Opcode, EVT 
VT, const SDLoc &dl,
     }
   }
 
-  if (!VT.isVector() && Opcode == ISD::MUL && LHSSB > InnerBitSize &&
-      RHSSB > InnerBitSize) {
+  if (!VT.isVector() && Opcode == ISD::MUL &&
+      DAG.ComputeNumSignBits(LHS) > InnerBitSize &&
+      DAG.ComputeNumSignBits(RHS) > InnerBitSize) {
     // The input values are both sign-extended.
     // TODO non-MUL case?
     if (MakeMUL_LOHI(LL, RL, Lo, Hi, true)) {


        
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