Author: Kazushi (Jam) Marukawa Date: 2021-01-08T18:49:17+09:00 New Revision: 12167632bc5cafee68da31592dae78a20a3e7e7a
URL: https://github.com/llvm/llvm-project/commit/12167632bc5cafee68da31592dae78a20a3e7e7a DIFF: https://github.com/llvm/llvm-project/commit/12167632bc5cafee68da31592dae78a20a3e7e7a.diff LOG: [VE] Add SVOB intrinsic instruction Add SVOB intrinsic instruction and a regression test. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D94279 Added: llvm/test/CodeGen/VE/VELIntrinsics/svob.ll Modified: llvm/include/llvm/IR/IntrinsicsVE.td llvm/lib/Target/VE/VEInstrIntrinsicVL.td Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/IntrinsicsVE.td b/llvm/include/llvm/IR/IntrinsicsVE.td index 1cb7a2e1eaf4..3a8eec6d4dd5 100644 --- a/llvm/include/llvm/IR/IntrinsicsVE.td +++ b/llvm/include/llvm/IR/IntrinsicsVE.td @@ -1,4 +1,10 @@ // Define intrinsics written by hand +// VEL Intrinsic instructions. +let TargetPrefix = "ve" in { + def int_ve_vl_svob : GCCBuiltin<"__builtin_ve_vl_svob">, + Intrinsic<[], [], [IntrHasSideEffects]>; +} + // Define intrinsics automatically generated include "llvm/IR/IntrinsicsVEVL.gen.td" diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td index 29365b327f27..b64d241cecfd 100644 --- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.td +++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.td @@ -2,6 +2,9 @@ // Define intrinsics written by hand +// SVOB pattern. +def : Pat<(int_ve_vl_svob), (SVOB)>; + // The lsv and lvs patterns def : Pat<(int_ve_vl_lsv_vvss v256f64:$pt, i32:$sy, i64:$sz), (LSVrr_v (INSERT_SUBREG (i64 (IMPLICIT_DEF)), i32:$sy, sub_i32), diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll b/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll new file mode 100644 index 000000000000..b835faecdc18 --- /dev/null +++ b/llvm/test/CodeGen/VE/VELIntrinsics/svob.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s + +;;; Test set vector out-of-order memory access boundary intrinsic instructions +;;; +;;; Note: +;;; We test SVOB instruction. + +; Function Attrs: nounwind +define fastcc void @svob_svob() { +; CHECK-LABEL: svob_svob: +; CHECK: # %bb.0: +; CHECK-NEXT: svob +; CHECK-NEXT: b.l.t (, %s10) + tail call void @llvm.ve.vl.svob() + ret void +} + +; Function Attrs: nounwind +declare void @llvm.ve.vl.svob() _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
