Author: Evandro Menezes Date: 2021-01-04T20:32:30-06:00 New Revision: d51d72bbb91bf1179e58a40998efb3be6bb1ca6f
URL: https://github.com/llvm/llvm-project/commit/d51d72bbb91bf1179e58a40998efb3be6bb1ca6f DIFF: https://github.com/llvm/llvm-project/commit/d51d72bbb91bf1179e58a40998efb3be6bb1ca6f.diff LOG: [RISCV] Rename RVV intrinsics class (NFC) Rename the class `RISCVUnaryAAMask` to `RISCVBinaryAAAMask`, since it has two input arguments. Added: Modified: llvm/include/llvm/IR/IntrinsicsRISCV.td Removed: ################################################################################ diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index ebb93ffcfc12..fe0d6b00a3c2 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -189,19 +189,19 @@ let TargetPrefix = "riscv" in { LLVMPointerType<LLVMMatchType<0>>, llvm_anyvector_ty, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], [NoCapture<ArgIndex<1>>, IntrWriteMem]>, RISCVVIntrinsic; - // For destination vector type is the same as first source vector (with mask). - // Input: (maskedoff, vector_in, mask, vl) - class RISCVUnaryAAMask - : Intrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, LLVMMatchType<0>, - LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], - [IntrNoMem]>, RISCVVIntrinsic; // For destination vector type is the same as first and second source vector. // Input: (vector_in, vector_in, vl) class RISCVBinaryAAANoMask : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty], [IntrNoMem]>, RISCVVIntrinsic; + // For destination vector type is the same as first and second source vector. + // Input: (vector_in, vector_in, vl) + class RISCVBinaryAAAMask + : Intrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, LLVMMatchType<0>, + LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty], + [IntrNoMem]>, RISCVVIntrinsic; // For destination vector type is the same as first source vector. // Input: (vector_in, vector_in/scalar_in, vl) class RISCVBinaryAAXNoMask @@ -704,7 +704,7 @@ let TargetPrefix = "riscv" in { defm vrgather : RISCVBinaryAAX; - def "int_riscv_vcompress_mask" : RISCVUnaryAAMask; + def "int_riscv_vcompress_mask" : RISCVBinaryAAAMask; defm vaaddu : RISCVSaturatingBinaryAAX; defm vaadd : RISCVSaturatingBinaryAAX; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
