Author: Simon Pilgrim Date: 2020-12-16T14:48:21Z New Revision: 553808d45620e12dad7dcab553d4444b74e6010d
URL: https://github.com/llvm/llvm-project/commit/553808d45620e12dad7dcab553d4444b74e6010d DIFF: https://github.com/llvm/llvm-project/commit/553808d45620e12dad7dcab553d4444b74e6010d.diff LOG: [X86] Rename reduction combiners to make it clearer whats happening. NFCI. Since these are all working on reduction patterns, actually use that term in the function name to make them easier to search for. At some point we're likely to start working with the ISD::VECREDUCE_* opcodes directly in the x86 backend, but that is still some way off. Added: Modified: llvm/lib/Target/X86/X86ISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 7be12238956e..2562cc2d37e1 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -39514,8 +39514,8 @@ static SDValue createPSADBW(SelectionDAG &DAG, const SDValue &Zext0, // Attempt to replace an min/max v8i16/v16i8 horizontal reduction with // PHMINPOSUW. -static SDValue combineHorizontalMinMaxResult(SDNode *Extract, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { +static SDValue combineMinMaxReduction(SDNode *Extract, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { // Bail without SSE41. if (!Subtarget.hasSSE41()) return SDValue(); @@ -39588,9 +39588,8 @@ static SDValue combineHorizontalMinMaxResult(SDNode *Extract, SelectionDAG &DAG, } // Attempt to replace an all_of/any_of/parity style horizontal reduction with a MOVMSK. -static SDValue combineHorizontalPredicateResult(SDNode *Extract, - SelectionDAG &DAG, - const X86Subtarget &Subtarget) { +static SDValue combinePredicateReduction(SDNode *Extract, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { // Bail without SSE2. if (!Subtarget.hasSSE2()) return SDValue(); @@ -40081,8 +40080,8 @@ static SDValue scalarizeExtEltFP(SDNode *ExtElt, SelectionDAG &DAG) { /// Try to convert a vector reduction sequence composed of binops and shuffles /// into horizontal ops. -static SDValue combineReductionToHorizontal(SDNode *ExtElt, SelectionDAG &DAG, - const X86Subtarget &Subtarget) { +static SDValue combineArithReduction(SDNode *ExtElt, SelectionDAG &DAG, + const X86Subtarget &Subtarget) { assert(ExtElt->getOpcode() == ISD::EXTRACT_VECTOR_ELT && "Unexpected caller"); // We need at least SSE2 to anything here. @@ -40282,7 +40281,7 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG, } // TODO - Remove this once we can handle the implicit zero-extension of - // X86ISD::PEXTRW/X86ISD::PEXTRB in combineHorizontalPredicateResult and + // X86ISD::PEXTRW/X86ISD::PEXTRB in combinePredicateReduction and // combineBasicSADPattern. return SDValue(); } @@ -40314,14 +40313,15 @@ static SDValue combineExtractVectorElt(SDNode *N, SelectionDAG &DAG, return SAD; // Attempt to replace an all_of/any_of horizontal reduction with a MOVMSK. - if (SDValue Cmp = combineHorizontalPredicateResult(N, DAG, Subtarget)) + if (SDValue Cmp = combinePredicateReduction(N, DAG, Subtarget)) return Cmp; // Attempt to replace min/max v8i16/v16i8 reductions with PHMINPOSUW. - if (SDValue MinMax = combineHorizontalMinMaxResult(N, DAG, Subtarget)) + if (SDValue MinMax = combineMinMaxReduction(N, DAG, Subtarget)) return MinMax; - if (SDValue V = combineReductionToHorizontal(N, DAG, Subtarget)) + // Attempt to optimize ADD/FADD/MUL reductions with HADD, promotion etc.. + if (SDValue V = combineArithReduction(N, DAG, Subtarget)) return V; if (SDValue V = scalarizeExtEltFP(N, DAG)) _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
