Author: Kazushi (Jam) Marukawa Date: 2020-12-15T01:16:56+09:00 New Revision: c9213e1b299579b37ad4a8c5d5516a10ddfb09b2
URL: https://github.com/llvm/llvm-project/commit/c9213e1b299579b37ad4a8c5d5516a10ddfb09b2 DIFF: https://github.com/llvm/llvm-project/commit/c9213e1b299579b37ad4a8c5d5516a10ddfb09b2.diff LOG: [VE] Correct addRegisterClass calls Correct addRegisterClass calls for vector mask registers. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D93212 Added: Modified: llvm/lib/Target/VE/VEISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp index 25a3910a48e4..f8235bb16622 100644 --- a/llvm/lib/Target/VE/VEISelLowering.cpp +++ b/llvm/lib/Target/VE/VEISelLowering.cpp @@ -73,8 +73,6 @@ bool VETargetLowering::CanLowerReturn( static const MVT AllVectorVTs[] = {MVT::v256i32, MVT::v512i32, MVT::v256i64, MVT::v256f32, MVT::v512f32, MVT::v256f64}; -static const MVT AllMaskVTs[] = {MVT::v256i1, MVT::v512i1}; - void VETargetLowering::initRegisterClasses() { // Set up the register classes. addRegisterClass(MVT::i32, &VE::I32RegClass); @@ -86,8 +84,8 @@ void VETargetLowering::initRegisterClasses() { if (Subtarget->enableVPU()) { for (MVT VecVT : AllVectorVTs) addRegisterClass(VecVT, &VE::V64RegClass); - for (MVT MaskVT : AllMaskVTs) - addRegisterClass(MaskVT, &VE::VMRegClass); + addRegisterClass(MVT::v256i1, &VE::VMRegClass); + addRegisterClass(MVT::v512i1, &VE::VM512RegClass); } } _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
