Author: Craig Topper Date: 2020-12-12T16:37:28-08:00 New Revision: 7977fee43cb8d26da21d8fb0b97671721ff00f40
URL: https://github.com/llvm/llvm-project/commit/7977fee43cb8d26da21d8fb0b97671721ff00f40 DIFF: https://github.com/llvm/llvm-project/commit/7977fee43cb8d26da21d8fb0b97671721ff00f40.diff LOG: [X86] Autogenerate complete checks. NFC Added: Modified: llvm/test/CodeGen/X86/splat-const.ll Removed: ################################################################################ diff --git a/llvm/test/CodeGen/X86/splat-const.ll b/llvm/test/CodeGen/X86/splat-const.ll index 19997b03ad5e..b2b27347f234 100644 --- a/llvm/test/CodeGen/X86/splat-const.ll +++ b/llvm/test/CodeGen/X86/splat-const.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mcpu=penryn | FileCheck %s --check-prefix=SSE ; RUN: llc < %s -mcpu=sandybridge | FileCheck %s --check-prefix=AVX ; RUN: llc < %s -mcpu=haswell | FileCheck %s --check-prefix=AVX2 @@ -7,14 +8,19 @@ target triple = "x86_64-unknown-unknown" define <4 x i32> @zero_vector() { ; SSE-LABEL: zero_vector: -; SSE: xorps %xmm0, %xmm0 -; SSE-NEXT: retq +; SSE: # %bb.0: +; SSE-NEXT: xorps %xmm0, %xmm0 +; SSE-NEXT: retq +; ; AVX-LABEL: zero_vector: -; AVX: vxorps %xmm0, %xmm0, %xmm0 -; AVX-NEXT: retq +; AVX: # %bb.0: +; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX-NEXT: retq +; ; AVX2-LABEL: zero_vector: -; AVX2: vxorps %xmm0, %xmm0, %xmm0 -; AVX2-NEXT: retq +; AVX2: # %bb.0: +; AVX2-NEXT: vxorps %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: retq %zero = insertelement <4 x i32> undef, i32 0, i32 0 %splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %splat @@ -26,14 +32,19 @@ define <4 x i32> @zero_vector() { ; However, this is not the current preferred lowering. define <4 x i32> @const_vector() { ; SSE-LABEL: const_vector: -; SSE: movaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42] -; SSE-NEXT: retq +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [42,42,42,42] +; SSE-NEXT: retq +; ; AVX-LABEL: const_vector: -; AVX: vmovaps {{.*}}, %xmm0 # xmm0 = [42,42,42,42] -; AVX-NEXT: retq +; AVX: # %bb.0: +; AVX-NEXT: vmovaps {{.*#+}} xmm0 = [42,42,42,42] +; AVX-NEXT: retq +; ; AVX2-LABEL: const_vector: -; AVX2: vbroadcastss {{[^%].*}}, %xmm0 -; AVX2-NEXT: retq +; AVX2: # %bb.0: +; AVX2-NEXT: vbroadcastss {{.*#+}} xmm0 = [42,42,42,42] +; AVX2-NEXT: retq %const = insertelement <4 x i32> undef, i32 42, i32 0 %splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %splat _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
