Author: Craig Topper Date: 2020-12-09T13:39:07-08:00 New Revision: 5ff5cf8e057782e3e648ecf5ccf1d9990b53ee90
URL: https://github.com/llvm/llvm-project/commit/5ff5cf8e057782e3e648ecf5ccf1d9990b53ee90 DIFF: https://github.com/llvm/llvm-project/commit/5ff5cf8e057782e3e648ecf5ccf1d9990b53ee90.diff LOG: [X86] Use APInt::isSignedIntN instead of isIntN for 64-bit ANDs in X86DAGToDAGISel::IsProfitableToFold Pretty sure we meant to be checking signed 32 immediates here rather than unsigned 32 bit. I suspect I messed this up because in MathExtras.h we have isIntN and isUIntN so isIntN differs in signedness depending on whether you're using APInt or plain integers. This fixes a case where we didn't fold a constant created by shrinkAndImmediate. Since shrinkAndImmediate doesn't topologically sort constants it creates, we can fail to convert the Constant to a TargetConstant. This leads to very strange behavior later. Fixes PR48458. Added: llvm/test/CodeGen/X86/pr48458.ll Modified: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp index de8c2f345fb5..a5cb078b2257 100644 --- a/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/llvm/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -616,7 +616,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { // best of both worlds. if (U->getOpcode() == ISD::AND && Imm->getAPIntValue().getBitWidth() == 64 && - Imm->getAPIntValue().isIntN(32)) + Imm->getAPIntValue().isSignedIntN(32)) return false; // If this really a zext_inreg that can be represented with a movzx diff --git a/llvm/test/CodeGen/X86/pr48458.ll b/llvm/test/CodeGen/X86/pr48458.ll new file mode 100644 index 000000000000..bca355961611 --- /dev/null +++ b/llvm/test/CodeGen/X86/pr48458.ll @@ -0,0 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s + +define i1 @foo(i64* %0) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %top +; CHECK-NEXT: movq (%rdi), %rax +; CHECK-NEXT: andq $-2147483648, %rax # imm = 0x80000000 +; CHECK-NEXT: sete %al +; CHECK-NEXT: retq +top: + %1 = load i64, i64* %0, !range !0 + %2 = icmp ult i64 %1, 2147483648 + ret i1 %2 +} + +!0 = !{i64 0, i64 10000000000} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
