Author: Simon Pilgrim Date: 2020-12-01T10:49:43Z New Revision: 551a20bad987272fa61c821205bfdc0cd2cd0bd0
URL: https://github.com/llvm/llvm-project/commit/551a20bad987272fa61c821205bfdc0cd2cd0bd0 DIFF: https://github.com/llvm/llvm-project/commit/551a20bad987272fa61c821205bfdc0cd2cd0bd0.diff LOG: [InstCombine][X86] Add test coverage showing failure to simplify addsub intrinsics to fadd/fsub If we only use odd/even lanes then we just need fadd/fsub ops Added: Modified: llvm/test/Transforms/InstCombine/X86/x86-addsub.ll Removed: ################################################################################ diff --git a/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll index 8ce578db2dd6..acf26c58faff 100644 --- a/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll +++ b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll @@ -10,9 +10,22 @@ declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) ; Demanded Elts ; - define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) { ; CHECK-LABEL: @elts_addsub_v2f64( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i32> <i32 1, i32 undef> +; CHECK-NEXT: [[TMP4:%.*]] = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> [[TMP0:%.*]], <2 x double> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <2 x double> [[TMP4]], i32 0 +; CHECK-NEXT: ret double [[TMP5]] +; + %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0> + %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 1, i32 1> + %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define double @elts_addsub_v2f64_sub(<2 x double> %0, <2 x double> %1) { +; CHECK-LABEL: @elts_addsub_v2f64_sub( ; CHECK-NEXT: [[TMP3:%.*]] = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> [[TMP0:%.*]], <2 x double> [[TMP1:%.*]]) ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <2 x double> [[TMP3]], i32 0 ; CHECK-NEXT: ret double [[TMP4]] @@ -41,6 +54,25 @@ define float @elts_addsub_v4f32(<4 x float> %0, <4 x float> %1) { ret float %8 } +define float @elts_addsub_v4f32_add(<4 x float> %0, <4 x float> %1) { +; CHECK-LABEL: @elts_addsub_v4f32_add( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP1:%.*]], <4 x float> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 1> +; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP3]], <4 x float> [[TMP4]]) +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x float> [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x float> [[TMP5]], i32 3 +; CHECK-NEXT: [[TMP8:%.*]] = fadd float [[TMP6]], [[TMP7]] +; CHECK-NEXT: ret float [[TMP8]] +; + %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4) + %6 = extractelement <4 x float> %5, i32 1 + %7 = extractelement <4 x float> %5, i32 3 + %8 = fadd float %6, %7 + ret float %8 +} + define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) { ; CHECK-LABEL: @elts_addsub_v4f64( ; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP0:%.*]], <4 x double> [[TMP1:%.*]]) @@ -58,6 +90,23 @@ define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) { ret double %8 } +define double @elts_addsub_v4f64_add(<4 x double> %0, <4 x double> %1) { +; CHECK-LABEL: @elts_addsub_v4f64_add( +; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP0:%.*]], <4 x double> [[TMP1:%.*]]) +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x double> [[TMP3]], i32 1 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x double> [[TMP3]], i32 3 +; CHECK-NEXT: [[TMP6:%.*]] = fadd double [[TMP4]], [[TMP5]] +; CHECK-NEXT: ret double [[TMP6]] +; + %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> + %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> + %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4) + %6 = extractelement <4 x double> %5, i32 1 + %7 = extractelement <4 x double> %5, i32 3 + %8 = fadd double %6, %7 + ret double %8 +} + define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) { ; CHECK-LABEL: @elts_addsub_v8f32( ; CHECK-NEXT: [[TMP3:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP0:%.*]], <8 x float> [[TMP1:%.*]]) @@ -75,6 +124,23 @@ define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) { ret float %8 } +define float @elts_addsub_v8f32_sub(<8 x float> %0, <8 x float> %1) { +; CHECK-LABEL: @elts_addsub_v8f32_sub( +; CHECK-NEXT: [[TMP3:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP0:%.*]], <8 x float> [[TMP1:%.*]]) +; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x float> [[TMP3]], i32 0 +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x float> [[TMP3]], i32 4 +; CHECK-NEXT: [[TMP6:%.*]] = fadd float [[TMP4]], [[TMP5]] +; CHECK-NEXT: ret float [[TMP6]] +; + %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> + %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> + %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4) + %6 = extractelement <8 x float> %5, i32 0 + %7 = extractelement <8 x float> %5, i32 4 + %8 = fadd float %6, %7 + ret float %8 +} + define void @PR46277(float %0, float %1, float %2, float %3, <4 x float> %4, float* %5) { ; CHECK-LABEL: @PR46277( ; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x float> undef, float [[TMP0:%.*]], i32 0 _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
