Author: Simon Pilgrim Date: 2020-11-30T13:40:51Z New Revision: 9c2b2952e422ba71c2afa9f6bb63ebf69fa5b702
URL: https://github.com/llvm/llvm-project/commit/9c2b2952e422ba71c2afa9f6bb63ebf69fa5b702 DIFF: https://github.com/llvm/llvm-project/commit/9c2b2952e422ba71c2afa9f6bb63ebf69fa5b702.diff LOG: [InstCombine][X86] Add addsub tests showing failure to simplify demandedelts (PR46277) Added: llvm/test/Transforms/InstCombine/X86/x86-addsub.ll Modified: Removed: ################################################################################ diff --git a/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll new file mode 100644 index 000000000000..67657354f599 --- /dev/null +++ b/llvm/test/Transforms/InstCombine/X86/x86-addsub.ll @@ -0,0 +1,85 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt < %s -instcombine -mtriple=x86_64-unknown-unknown -S | FileCheck %s + +declare <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double>, <2 x double>) +declare <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float>, <4 x float>) +declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) +declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) + +; +; Demanded Elts +; + + +define double @elts_addsub_v2f64(<2 x double> %0, <2 x double> %1) { +; CHECK-LABEL: @elts_addsub_v2f64( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[TMP0:%.*]], <2 x double> undef, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x double> [[TMP1:%.*]], <2 x double> undef, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP5:%.*]] = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> [[TMP3]], <2 x double> [[TMP4]]) +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <2 x double> [[TMP5]], i32 0 +; CHECK-NEXT: ret double [[TMP6]] +; + %3 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> <i32 0, i32 0> + %4 = shufflevector <2 x double> %1, <2 x double> undef, <2 x i32> <i32 0, i32 0> + %5 = tail call <2 x double> @llvm.x86.sse3.addsub.pd(<2 x double> %3, <2 x double> %4) + %6 = extractelement <2 x double> %5, i32 0 + ret double %6 +} + +define float @elts_addsub_v4f32(<4 x float> %0, <4 x float> %1) { +; CHECK-LABEL: @elts_addsub_v4f32( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[TMP0:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x float> [[TMP1:%.*]], <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> +; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> [[TMP3]], <4 x float> [[TMP4]]) +; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x float> [[TMP5]], <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> +; CHECK-NEXT: [[TMP7:%.*]] = fadd <4 x float> [[TMP5]], [[TMP6]] +; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x float> [[TMP7]], i32 0 +; CHECK-NEXT: ret float [[TMP8]] +; + %3 = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + %4 = shufflevector <4 x float> %1, <4 x float> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1> + %5 = tail call <4 x float> @llvm.x86.sse3.addsub.ps(<4 x float> %3, <4 x float> %4) + %6 = shufflevector <4 x float> %5, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> + %7 = fadd <4 x float> %5, %6 + %8 = extractelement <4 x float> %7, i32 0 + ret float %8 +} + +define double @elts_addsub_v4f64(<4 x double> %0, <4 x double> %1) { +; CHECK-LABEL: @elts_addsub_v4f64( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x double> [[TMP0:%.*]], <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x double> [[TMP1:%.*]], <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> +; CHECK-NEXT: [[TMP5:%.*]] = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> [[TMP3]], <4 x double> [[TMP4]]) +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x double> [[TMP5]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x double> [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = fadd double [[TMP6]], [[TMP7]] +; CHECK-NEXT: ret double [[TMP8]] +; + %3 = shufflevector <4 x double> %0, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> + %4 = shufflevector <4 x double> %1, <4 x double> undef, <4 x i32> <i32 0, i32 1, i32 3, i32 3> + %5 = tail call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %3, <4 x double> %4) + %6 = extractelement <4 x double> %5, i32 0 + %7 = extractelement <4 x double> %5, i32 1 + %8 = fadd double %6, %7 + ret double %8 +} + +define float @elts_addsub_v8f32(<8 x float> %0, <8 x float> %1) { +; CHECK-LABEL: @elts_addsub_v8f32( +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x float> [[TMP0:%.*]], <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> +; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x float> [[TMP1:%.*]], <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> +; CHECK-NEXT: [[TMP5:%.*]] = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> [[TMP3]], <8 x float> [[TMP4]]) +; CHECK-NEXT: [[TMP6:%.*]] = extractelement <8 x float> [[TMP5]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <8 x float> [[TMP5]], i32 1 +; CHECK-NEXT: [[TMP8:%.*]] = fadd float [[TMP6]], [[TMP7]] +; CHECK-NEXT: ret float [[TMP8]] +; + %3 = shufflevector <8 x float> %0, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> + %4 = shufflevector <8 x float> %1, <8 x float> undef, <8 x i32> <i32 0, i32 1, i32 0, i32 1, i32 4, i32 4, i32 4, i32 4> + %5 = tail call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %3, <8 x float> %4) + %6 = extractelement <8 x float> %5, i32 0 + %7 = extractelement <8 x float> %5, i32 1 + %8 = fadd float %6, %7 + ret float %8 +} + _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
