Author: Craig Topper Date: 2020-11-22T00:46:12-08:00 New Revision: 84b8222705c32c15818a9093b8217027f129f218
URL: https://github.com/llvm/llvm-project/commit/84b8222705c32c15818a9093b8217027f129f218 DIFF: https://github.com/llvm/llvm-project/commit/84b8222705c32c15818a9093b8217027f129f218.diff LOG: [RISCV] Use separate Lo and Hi MemOperands when expanding BuildPairF64Pseudo and SplitF64Pseudo. We generate two 4 byte loads or two stores as part of the expansion. Previously the MemOperand was set the same for both to cover the full 8 bytes. Now we set a separate 4 byte mem operand for each with a 4 byte offset for the high part. Added: Modified: llvm/lib/Target/RISCV/RISCVISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index bbb76d39ab7a..0ae3c7b768a5 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -1520,17 +1520,19 @@ static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI, TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC, RI); - MachineMemOperand *MMO = - MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), - MachineMemOperand::MOLoad, 8, Align(8)); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = + MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( + MPI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8)); BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg) .addFrameIndex(FI) .addImm(0) - .addMemOperand(MMO); + .addMemOperand(MMOLo); BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) .addFrameIndex(FI) .addImm(4) - .addMemOperand(MMO); + .addMemOperand(MMOHi); MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; } @@ -1550,19 +1552,21 @@ static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI, const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass; int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF); - MachineMemOperand *MMO = - MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), - MachineMemOperand::MOStore, 8, Align(8)); + MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI); + MachineMemOperand *MMOLo = + MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(8)); + MachineMemOperand *MMOHi = MF.getMachineMemOperand( + MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8)); BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill())) .addFrameIndex(FI) .addImm(0) - .addMemOperand(MMO); + .addMemOperand(MMOLo); BuildMI(*BB, MI, DL, TII.get(RISCV::SW)) .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) .addFrameIndex(FI) .addImm(4) - .addMemOperand(MMO); + .addMemOperand(MMOHi); TII.loadRegFromStackSlot(*BB, MI, DstReg, FI, DstRC, RI); MI.eraseFromParent(); // The pseudo instruction is gone now. return BB; _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
