Author: Evandro Menezes Date: 2020-09-21T18:24:53-05:00 New Revision: 394d02016705e4b0fdfaa34c53be695f3f61922d
URL: https://github.com/llvm/llvm-project/commit/394d02016705e4b0fdfaa34c53be695f3f61922d DIFF: https://github.com/llvm/llvm-project/commit/394d02016705e4b0fdfaa34c53be695f3f61922d.diff LOG: [RISCV] Do not mandate scheduling for CSR instructions Scheduling information is of little value when they may disrupt the pipeline. This patch allows omitting the scheduling information for CSR instructions while still setting `SchedMachineModel::CompleteModel`. For specific cases, any scheduling information added will be used by the scheduler. Differential revision: https://reviews.llvm.org/D85366 Added: Modified: llvm/lib/Target/RISCV/RISCVInstrInfo.td Removed: ################################################################################ diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index 2697c9640bc6..878f7ad5d61d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -368,12 +368,14 @@ class ALU_rr<bits<7> funct7, bits<3> funct3, string opcodestr> : RVInstR<funct7, funct3, OPC_OP, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">; -let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in +let hasNoSchedulingInfo = 1, + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in class CSR_ir<bits<3> funct3, string opcodestr> : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, GPR:$rs1), opcodestr, "$rd, $imm12, $rs1">, Sched<[WriteCSR, ReadCSR]>; -let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in +let hasNoSchedulingInfo = 1, + hasSideEffects = 1, mayLoad = 0, mayStore = 0 in class CSR_ii<bits<3> funct3, string opcodestr> : RVInstI<funct3, OPC_SYSTEM, (outs GPR:$rd), (ins csr_sysreg:$imm12, uimm5:$rs1), _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
