Author: Thomas Lively Date: 2020-09-07T19:23:56+02:00 New Revision: 8399522c96a94bfb7c1cbf4df2bed0b3d826fbf6
URL: https://github.com/llvm/llvm-project/commit/8399522c96a94bfb7c1cbf4df2bed0b3d826fbf6 DIFF: https://github.com/llvm/llvm-project/commit/8399522c96a94bfb7c1cbf4df2bed0b3d826fbf6.diff LOG: [WebAssembly] Fix incorrect assumption of simple value types Fixes PR47375, in which an assertion was triggering because WebAssemblyTargetLowering::isVectorLoadExtDesirable was improperly assuming the use of simple value types. Differential Revision: https://reviews.llvm.org/D87110 (cherry picked from commit caee15a0ed52471bd329d01dc253ec9be3936c6d) Added: llvm/test/CodeGen/WebAssembly/pr47375.ll Modified: llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp index a9b9eceb41304..925636c823219 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp @@ -601,8 +601,8 @@ bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT, } bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const { - MVT ExtT = ExtVal.getSimpleValueType(); - MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0); + EVT ExtT = ExtVal.getValueType(); + EVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getValueType(0); return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) || (ExtT == MVT::v4i32 && MemT == MVT::v4i16) || (ExtT == MVT::v2i64 && MemT == MVT::v2i32); diff --git a/llvm/test/CodeGen/WebAssembly/pr47375.ll b/llvm/test/CodeGen/WebAssembly/pr47375.ll new file mode 100644 index 0000000000000..4c04631f26b11 --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/pr47375.ll @@ -0,0 +1,36 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s | FileCheck %s + +target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" +target triple = "wasm32-unknown-unknown" + +; Regression test for pr47375, in which an assertion was triggering +; because WebAssemblyTargetLowering::isVectorLoadExtDesirable was +; improperly assuming the use of simple value types. + +define void @sext_vec() { +; CHECK-LABEL: sext_vec: +; CHECK: .functype sext_vec () -> () +; CHECK-NEXT: .local i32 +; CHECK-NEXT: # %bb.0: +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.load8_u 0 +; CHECK-NEXT: local.set 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.const 0 +; CHECK-NEXT: i32.store8 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: i32.const 7 +; CHECK-NEXT: i32.shl +; CHECK-NEXT: i32.or +; CHECK-NEXT: i32.const 7175 +; CHECK-NEXT: i32.and +; CHECK-NEXT: i32.store16 0 +; CHECK-NEXT: # fallthrough-return + %L1 = load <2 x i3>, <2 x i3>* undef, align 2 + %zext = zext <2 x i3> %L1 to <2 x i10> + store <2 x i10> %zext, <2 x i10>* undef, align 4 + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
