Author: Kang Zhang Date: 2020-09-01T17:15:52+02:00 New Revision: 7569e8c696288cd9c9409936b4fe9b846d0bd0b7
URL: https://github.com/llvm/llvm-project/commit/7569e8c696288cd9c9409936b4fe9b846d0bd0b7 DIFF: https://github.com/llvm/llvm-project/commit/7569e8c696288cd9c9409936b4fe9b846d0bd0b7.diff LOG: [PowerPC] Set v1i128 to expand for SETCC to avoid crash Summary: PPC only supports the instruction selection for v16i8, v8i16, v4i32, v2i64, v4f32 and v2f64 for ISD::SETCC, don't support the v1i128, so v1i128 for ISD::SETCC will crash. This patch is to set v1i128 to expand to avoid crash. Reviewed By: steven.zhang Differential Revision: https://reviews.llvm.org/D84238 (cherry picked from commit 802c043078ad653aca131648a130b59f041df0b5) Added: llvm/test/CodeGen/PowerPC/setcc-vector.ll Modified: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 5c1a4cb16568..2f50c52c90a1 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -920,6 +920,8 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM, setOperationAction(ISD::SUB, MVT::v2i64, Expand); } + setOperationAction(ISD::SETCC, MVT::v1i128, Expand); + setOperationAction(ISD::LOAD, MVT::v2i64, Promote); AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64); setOperationAction(ISD::STORE, MVT::v2i64, Promote); diff --git a/llvm/test/CodeGen/PowerPC/setcc-vector.ll b/llvm/test/CodeGen/PowerPC/setcc-vector.ll new file mode 100644 index 000000000000..5917ccabf84e --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/setcc-vector.ll @@ -0,0 +1,49 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR9 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR8 %s +; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-unknown-unknown \ +; RUN: -ppc-asm-full-reg-names < %s | FileCheck -check-prefixes=CHECK-PWR7 %s + +define <1 x i64> @setcc_v1i128(<1 x i128> %a) { +; CHECK-PWR9-LABEL: setcc_v1i128: +; CHECK-PWR9: # %bb.0: # %entry +; CHECK-PWR9-NEXT: mfvsrld r3, vs34 +; CHECK-PWR9-NEXT: cmpldi r3, 35708 +; CHECK-PWR9-NEXT: mfvsrd r3, vs34 +; CHECK-PWR9-NEXT: cmpdi cr1, r3, 0 +; CHECK-PWR9-NEXT: li r3, 1 +; CHECK-PWR9-NEXT: crnand 4*cr5+lt, 4*cr1+eq, lt +; CHECK-PWR9-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-PWR9-NEXT: blr +; +; CHECK-PWR8-LABEL: setcc_v1i128: +; CHECK-PWR8: # %bb.0: # %entry +; CHECK-PWR8-NEXT: xxswapd vs0, vs34 +; CHECK-PWR8-NEXT: mfvsrd r3, vs34 +; CHECK-PWR8-NEXT: cmpdi r3, 0 +; CHECK-PWR8-NEXT: li r3, 1 +; CHECK-PWR8-NEXT: mffprd r4, f0 +; CHECK-PWR8-NEXT: cmpldi cr1, r4, 35708 +; CHECK-PWR8-NEXT: crnand 4*cr5+lt, eq, 4*cr1+lt +; CHECK-PWR8-NEXT: isel r3, 0, r3, 4*cr5+lt +; CHECK-PWR8-NEXT: blr +; +; CHECK-PWR7-LABEL: setcc_v1i128: +; CHECK-PWR7: # %bb.0: # %entry +; CHECK-PWR7-NEXT: li r5, 0 +; CHECK-PWR7-NEXT: cntlzd r3, r3 +; CHECK-PWR7-NEXT: ori r5, r5, 35708 +; CHECK-PWR7-NEXT: rldicl r3, r3, 58, 63 +; CHECK-PWR7-NEXT: subc r5, r4, r5 +; CHECK-PWR7-NEXT: subfe r4, r4, r4 +; CHECK-PWR7-NEXT: neg r4, r4 +; CHECK-PWR7-NEXT: and r3, r3, r4 +; CHECK-PWR7-NEXT: blr +entry: + %0 = icmp ult <1 x i128> %a, <i128 35708> + %1 = zext <1 x i1> %0 to <1 x i64> + ret <1 x i64> %1 +} + _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
