Author: Kristof Beyls Date: 2020-08-31T14:10:54+02:00 New Revision: d98e4c0d9a3585e2302c717beea9b9d03df9663a
URL: https://github.com/llvm/llvm-project/commit/d98e4c0d9a3585e2302c717beea9b9d03df9663a DIFF: https://github.com/llvm/llvm-project/commit/d98e4c0d9a3585e2302c717beea9b9d03df9663a.diff LOG: Add a few more release notes for ARM and AArch64. Added: Modified: llvm/docs/ReleaseNotes.rst Removed: ################################################################################ diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index c7ca861dbc34..8171f9d990c9 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -119,11 +119,26 @@ Changes to the AArch64 Backend ``00bet5``). For more information, see the ``clang`` 11 release notes. +* Added support for Armv8.6-A: + + Assembly support for the following extensions: + - Enhanced Counter Virtualization (ARMv8.6-ECV). + - Fine Grained Traps (ARMv8.6-FGT). + - Activity Monitors virtualization (ARMv8.6-AMU). + - Data gathering hint (ARMv8.0-DGH). + + Assembly and intrinsics support for the Armv8.6-A Matrix Multiply extension + for Neon and SVE vectors. + + Support for the ARMv8.2-BF16 BFloat16 extension. This includes a new C-level + storage-only `__bf16` type, a `BFloat` IR type, a `bf16` MVT, and assembly + and intrinsics support. + +* Added support for Cortex-A34, Cortex-A77, Cortex-A78 and Cortex-X1 cores. + Changes to the ARM Backend -------------------------- -During this release ... - * Implemented C-language intrinsics for the full Arm v8.1-M MVE instruction set. ``<arm_mve.h>`` now supports the complete API defined in the Arm C Language Extensions. @@ -139,6 +154,19 @@ During this release ... default may wish to specify ``-fno-omit-frame-pointer`` to get the old behavior. This improves compatibility with GCC. +* Added support for Armv8.6-A: + + Assembly and intrinsics support for the Armv8.6-A Matrix Multiply extension + for Neon vectors. + + Support for the ARMv8.2-AA32BF16 BFloat16 extension. This includes a new + C-level storage-only `__bf16` type, a `BFloat` IR type, a `bf16` MVT, and + assembly and intrinsics support. + +* Added support for CMSE. + +* Added support for Cortex-M55, Cortex-A77, Cortex-A78 and Cortex-X1 cores. + Changes to the MIPS Target -------------------------- _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
