Author: Craig Topper Date: 2020-08-27T21:19:58-07:00 New Revision: 2eab0b4f20aa192ba5ca8492c20aeae85b44e70b
URL: https://github.com/llvm/llvm-project/commit/2eab0b4f20aa192ba5ca8492c20aeae85b44e70b DIFF: https://github.com/llvm/llvm-project/commit/2eab0b4f20aa192ba5ca8492c20aeae85b44e70b.diff LOG: [X86] Update release notes. Added: Modified: llvm/docs/ReleaseNotes.rst Removed: ################################################################################ diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 49b1a040a393..c7ca861dbc34 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -167,6 +167,16 @@ During this release ... avx512bw otherwise they would split into multiple YMM registers. This means vXi16/vXi8 vectors are consistently treated the same as vXi32/vXi64/vXf64/vXf32 vectors of the same total width. +* Support was added for Intel AMX instructions. +* Support was added for TSXLDTRK instructions. +* A pass was added for mitigating the Load Value Injection vulnerability. +* The Speculative Execution Side Effect Suppression pass was added which can + be used to as a last resort mitigation for speculative execution related + CPU vulnerabilities. +* Improved recognition of boolean vector reductions with better MOVMSKB/PTEST + handling +* Exteded recognition of rotation patterns to handle funnel shift as well, + allowing us to remove the existing x86-specific SHLD/SHRD combine. Changes to the AMDGPU Target ----------------------------- _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
