Author: Francesco Petrogalli Date: 2020-08-26T15:41:59+01:00 New Revision: 6f2ba83779c8055a58f1cc9ee33686a8109ff33a
URL: https://github.com/llvm/llvm-project/commit/6f2ba83779c8055a58f1cc9ee33686a8109ff33a DIFF: https://github.com/llvm/llvm-project/commit/6f2ba83779c8055a58f1cc9ee33686a8109ff33a.diff LOG: [release][SVE] Move notes for SVE ACLE to the release notes of clang. Added: Modified: clang/docs/ReleaseNotes.rst llvm/docs/ReleaseNotes.rst Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 6f336088750f..a8fde6b452d0 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -90,6 +90,60 @@ Non-comprehensive list of changes in this release a fixed hashing algorithm that prevents some collision when loading out-of-date profile informations. Clang can still read old profile files. +- Clang adds support for the following macros that enable the + C-intrinsics from the `Arm C language extensions for SVE + <https://developer.arm.com/documentation/100987/>`_ (version + ``00bet5``, see section 2.1 for the list of intrinsics associated to + each macro): + + + ================================= ================= + Preprocessor macro Target feature + ================================= ================= + ``__ARM_FEATURE_SVE`` ``+sve`` + ``__ARM_FEATURE_SVE_BF16`` ``+sve+bf16`` + ``__ARM_FEATURE_SVE_MATMUL_FP32`` ``+sve+f32mm`` + ``__ARM_FEATURE_SVE_MATMUL_FP64`` ``+sve+f64mm`` + ``__ARM_FEATURE_SVE_MATMUL_INT8`` ``+sve+i8mm`` + ``__ARM_FEATURE_SVE2`` ``+sve2`` + ``__ARM_FEATURE_SVE2_AES`` ``+sve2-aes`` + ``__ARM_FEATURE_SVE2_BITPERM`` ``+sve2-bitperm`` + ``__ARM_FEATURE_SVE2_SHA3`` ``+sve2-sha3`` + ``__ARM_FEATURE_SVE2_SM4`` ``+sve2-sm4`` + ================================= ================= + + The macros enable users to write C/C++ `Vector Length Agnostic + (VLA)` loops, that can be executed on any CPU that implements the + underlying instructions supported by the C intrinsics, independently + of the hardware vector register size. + + For example, the ``__ARM_FEATURE_SVE`` macro is enabled when + targeting AArch64 code generation by setting ``-march=armv8-a+sve`` + on the command line. + + .. code-block:: c + :caption: Example of VLA addition of two arrays with SVE ACLE. + + // Compile with: + // `clang++ -march=armv8a+sve ...` (for c++) + // `clang -stc=c11 -march=armv8a+sve ...` (for c) + #include <arm_sve.h> + + void VLA_add_arrays(double *x, double *y, double *out, unsigned N) { + for (unsigned i = 0; i < N; i += svcntd()) { + svbool_t Pg = svwhilelt_b64(i, N); + svfloat64_t vx = svld1(Pg, &x[i]); + svfloat64_t vy = svld1(Pg, &y[i]); + svfloat64_t vout = svadd_x(Pg, vx, vy); + svst1(Pg, &out[i], vout); + } + } + + Please note that support for lazy binding of SVE function calls is + incomplete. When you interface user code with SVE functions that are + provided through shared libraries, avoid using lazy binding. If you + use lazy binding, the results could be corrupted. + New Compiler Flags ------------------ diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 6c92c1224238..5bbdea65c3e7 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -106,59 +106,11 @@ Changes to the AArch64 Backend * Clearly error out on unsupported relocations when targeting COFF, instead of silently accepting some (without being able to do what was requested). -* Clang adds support for the following macros that enable the - C-intrinsics from the `Arm C language extensions for SVE +* Implemented codegen support for the SVE C-language intrinsics + documented in `Arm C Language Extensions (ACLE) for SVE <https://developer.arm.com/documentation/100987/>`_ (version - ``00bet5``, see section 2.1 for the list of intrinsics associated to - each macro): - - - ================================= ================= - Preprocessor macro Target feature - ================================= ================= - ``__ARM_FEATURE_SVE`` ``+sve`` - ``__ARM_FEATURE_SVE_BF16`` ``+sve+bf16`` - ``__ARM_FEATURE_SVE_MATMUL_FP32`` ``+sve+f32mm`` - ``__ARM_FEATURE_SVE_MATMUL_FP64`` ``+sve+f64mm`` - ``__ARM_FEATURE_SVE_MATMUL_INT8`` ``+sve+i8mm`` - ``__ARM_FEATURE_SVE2`` ``+sve2`` - ``__ARM_FEATURE_SVE2_AES`` ``+sve2-aes`` - ``__ARM_FEATURE_SVE2_BITPERM`` ``+sve2-bitperm`` - ``__ARM_FEATURE_SVE2_SHA3`` ``+sve2-sha3`` - ``__ARM_FEATURE_SVE2_SM4`` ``+sve2-sm4`` - ================================= ================= - - The macros enable users to write C/C++ `Vector Length Agnostic - (VLA)` loops, that can be executed on any CPU that implements the - underlying instructions supported by the C intrinsics, independently - of the hardware vector register size. - - For example, the ``__ARM_FEATURE_SVE`` macro is enabled when - targeting AArch64 code generation by setting ``-march=armv8-a+sve`` - on the command line. - - .. code-block:: c - :caption: Example of VLA addition of two arrays with SVE ACLE. - - // Compile with: - // `clang++ -march=armv8a+sve ...` (for c++) - // `clang -stc=c11 -march=armv8a+sve ...` (for c) - #include <arm_sve.h> - - void VLA_add_arrays(double *x, double *y, double *out, unsigned N) { - for (unsigned i = 0; i < N; i += svcntd()) { - svbool_t Pg = svwhilelt_b64(i, N); - svfloat64_t vx = svld1(Pg, &x[i]); - svfloat64_t vy = svld1(Pg, &y[i]); - svfloat64_t vout = svadd_x(Pg, vx, vy); - svst1(Pg, &out[i], vout); - } - } - - Please note that support for lazy binding of SVE function calls is - incomplete. When you interface user code with SVE functions that are - provided through shared libraries, avoid using lazy binding. If you - use lazy binding, the results could be corrupted. + ``00bet5``). For more information, see the ``clang`` 11 release + notes. Changes to the ARM Backend -------------------------- _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
