Author: David Sherwood Date: 2020-08-17T13:58:11+02:00 New Revision: 2d52adc4ade0d194a3341742b01d088c5fdd70c6
URL: https://github.com/llvm/llvm-project/commit/2d52adc4ade0d194a3341742b01d088c5fdd70c6 DIFF: https://github.com/llvm/llvm-project/commit/2d52adc4ade0d194a3341742b01d088c5fdd70c6.diff LOG: [SVE][CodeGen] Fix bug with store of unpacked FP scalable vectors Fixed an incorrect pattern in lib/Target/AArch64/AArch64SVEInstrInfo.td for storing out <vscale x 2 x f32> unpacked scalable vectors. Added a couple of tests to test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll Differential Revision: https://reviews.llvm.org/D85441 (cherry picked from commit 0905d9f31ead399d054c5d2a2c353e690f5c8daa) Added: Modified: llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll Removed: ################################################################################ diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 3449a8bd16d2..4f29f2f18185 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1765,7 +1765,7 @@ multiclass sve_prefetch<SDPatternOperator prefetch, ValueType PredTy, Instructio defm : unpred_store< store, nxv4f16, ST1H_S_IMM, PTRUE_S>; defm : unpred_store< store, nxv2f16, ST1H_D_IMM, PTRUE_D>; defm : unpred_store< store, nxv4f32, ST1W_IMM, PTRUE_S>; - defm : unpred_store< store, nxv4f32, ST1W_D_IMM, PTRUE_D>; + defm : unpred_store< store, nxv2f32, ST1W_D_IMM, PTRUE_D>; defm : unpred_store< store, nxv2f64, ST1D_IMM, PTRUE_D>; multiclass unpred_load<PatFrag Load, ValueType Ty, Instruction RegImmInst, diff --git a/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll b/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll index 1d81a586826f..e24db77b682e 100644 --- a/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll +++ b/llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll @@ -104,3 +104,32 @@ define void @st1d_inbound(<vscale x 2 x i64> %data, <vscale x 2 x i64>* %a) { store <vscale x 2 x i64> %data, <vscale x 2 x i64>* %base ret void } + + +; Splat stores of unpacked FP scalable vectors + +define void @store_nxv2f32(<vscale x 2 x float>* %out) { +; CHECK-LABEL: store_nxv2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov z0.s, #1.00000000 +; CHECK-NEXT: ptrue p0.d +; CHECK-NEXT: st1w { z0.d }, p0, [x0] +; CHECK-NEXT: ret + %ins = insertelement <vscale x 2 x float> undef, float 1.0, i32 0 + %splat = shufflevector <vscale x 2 x float> %ins, <vscale x 2 x float> undef, <vscale x 2 x i32> zeroinitializer + store <vscale x 2 x float> %splat, <vscale x 2 x float>* %out + ret void +} + +define void @store_nxv4f16(<vscale x 4 x half>* %out) { +; CHECK-LABEL: store_nxv4f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov z0.h, #1.00000000 +; CHECK-NEXT: ptrue p0.s +; CHECK-NEXT: st1h { z0.s }, p0, [x0] +; CHECK-NEXT: ret + %ins = insertelement <vscale x 4 x half> undef, half 1.0, i32 0 + %splat = shufflevector <vscale x 4 x half> %ins, <vscale x 4 x half> undef, <vscale x 4 x i32> zeroinitializer + store <vscale x 4 x half> %splat, <vscale x 4 x half>* %out + ret void +} _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
