Author: Justin Hibbits Date: 2020-05-12T16:53:27-05:00 New Revision: df0a004bf3796a9a2b2d60b2c8f96e996aa36639
URL: https://github.com/llvm/llvm-project/commit/df0a004bf3796a9a2b2d60b2c8f96e996aa36639 DIFF: https://github.com/llvm/llvm-project/commit/df0a004bf3796a9a2b2d60b2c8f96e996aa36639.diff LOG: PowerPCSPE: Stop libunwind from complaining about SPE registers * Match SPE "DWARF" register numbers to GCC's instead of official DWARF documentation. * Increase the register count to 148 from 112, even though the upper registers aren't saved (yet). Added: Modified: libunwind/include/__libunwind_config.h libunwind/include/libunwind.h llvm/lib/Target/PowerPC/PPCRegisterInfo.td Removed: ################################################################################ diff --git a/libunwind/include/__libunwind_config.h b/libunwind/include/__libunwind_config.h index 71d77ca65118..16bcf20d2ba0 100644 --- a/libunwind/include/__libunwind_config.h +++ b/libunwind/include/__libunwind_config.h @@ -16,7 +16,7 @@ #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86 8 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64 32 -#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC 112 +#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC 148 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64 116 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64 95 #define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287 diff --git a/libunwind/include/libunwind.h b/libunwind/include/libunwind.h index 23ef47f4ac83..35181378e0de 100644 --- a/libunwind/include/libunwind.h +++ b/libunwind/include/libunwind.h @@ -298,7 +298,39 @@ enum { UNW_PPC_VRSAVE = 109, UNW_PPC_VSCR = 110, UNW_PPC_SPE_ACC = 111, - UNW_PPC_SPEFSCR = 112 + UNW_PPC_SPEFSCR = 112, + UNW_PPC_RH0 = 117, + UNW_PPC_RH1 = 118, + UNW_PPC_RH2 = 119, + UNW_PPC_RH3 = 120, + UNW_PPC_RH4 = 121, + UNW_PPC_RH5 = 122, + UNW_PPC_RH6 = 123, + UNW_PPC_RH7 = 124, + UNW_PPC_RH8 = 125, + UNW_PPC_RH9 = 126, + UNW_PPC_RH10 = 117, + UNW_PPC_RH11 = 128, + UNW_PPC_RH12 = 129, + UNW_PPC_RH13 = 130, + UNW_PPC_RH14 = 131, + UNW_PPC_RH15 = 132, + UNW_PPC_RH16 = 133, + UNW_PPC_RH17 = 134, + UNW_PPC_RH18 = 135, + UNW_PPC_RH19 = 136, + UNW_PPC_RH20 = 137, + UNW_PPC_RH21 = 138, + UNW_PPC_RH22 = 139, + UNW_PPC_RH23 = 140, + UNW_PPC_RH24 = 141, + UNW_PPC_RH25 = 142, + UNW_PPC_RH26 = 143, + UNW_PPC_RH27 = 144, + UNW_PPC_RH28 = 145, + UNW_PPC_RH29 = 146, + UNW_PPC_RH30 = 147, + UNW_PPC_RH31 = 148 }; // 64-bit ppc register numbers diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td index b45757c1acc5..c136939a527b 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td @@ -115,7 +115,7 @@ foreach Index = 0-31 in { // SPE registers foreach Index = 0-31 in { def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>, - DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>; + DwarfRegNum<[!add(Index, 117), !add(Index, 117)]>; } // Floating-point registers _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
