Author: Justin Hibbits Date: 2020-05-12T16:53:26-05:00 New Revision: 33e552d43617201799637faeabfdbe80e9d80a1b
URL: https://github.com/llvm/llvm-project/commit/33e552d43617201799637faeabfdbe80e9d80a1b DIFF: https://github.com/llvm/llvm-project/commit/33e552d43617201799637faeabfdbe80e9d80a1b.diff LOG: PowerPC: Fix SPE f64 VAARG handling. SPE follows soft-float ABI for doubles, including VAARG passing. For soft-float, doubles are bitcast to i64, but for SPE they are not, so we need to perform GPR alignment explicitly for SPE f64. Added: Modified: llvm/lib/Target/PowerPC/PPCISelLowering.cpp Removed: ################################################################################ diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp index 4a733986412c..83a119fec86b 100644 --- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp @@ -3229,7 +3229,7 @@ SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { VAListPtr, MachinePointerInfo(SV), MVT::i8); InChain = GprIndex.getValue(1); - if (VT == MVT::i64) { + if (VT == MVT::i64 || (hasSPE() && VT == MVT::f64)) { // Check if GprIndex is even SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, DAG.getConstant(1, dl, MVT::i32)); _______________________________________________ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
